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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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arm64: dts: juno: Update entries to match latest coresight bindings
Switch to updated coresight bindings for Juno platforms. Cc: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> [sudeep.holla: minor modifications to patch title] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This commit is contained in:
Suzuki K Poulose
Sudeep Holla
parent
5b394b2ddf
commit
41af6cbfa1
@ -115,22 +115,17 @@ etf@20010000 { /* etf0 */
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* input port */
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port@0 {
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reg = <0>;
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in-ports {
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port {
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etf0_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&main_funnel_out_port>;
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};
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};
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};
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/* output port */
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port@1 {
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reg = <0>;
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out-ports {
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port {
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etf0_out_port: endpoint {
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};
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};
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@ -144,13 +139,14 @@ tpiu@20030000 {
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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in-ports {
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port {
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tpiu_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out_port0>;
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};
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};
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};
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};
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/* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
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main_funnel: funnel@20040000 {
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@ -160,31 +156,29 @@ main_funnel: funnel@20040000 {
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* output port */
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port@0 {
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reg = <0>;
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out-ports {
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port {
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main_funnel_out_port: endpoint {
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remote-endpoint = <&etf0_in_port>;
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};
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};
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};
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/* input ports */
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port@1 {
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main_funnel_in_ports: in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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main_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&cluster0_funnel_out_port>;
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};
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};
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port@2 {
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port@1 {
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reg = <1>;
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main_funnel_in_port1: endpoint {
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slave-mode;
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remote-endpoint = <&cluster1_funnel_out_port>;
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};
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};
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@ -199,13 +193,14 @@ etr@20070000 {
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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in-ports {
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port {
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etr_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out_port1>;
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};
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};
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};
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};
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stm@20100000 {
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compatible = "arm,coresight-stm", "arm,primecell";
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@ -216,11 +211,13 @@ stm@20100000 {
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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stm_out_port: endpoint {
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};
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};
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};
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};
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cpu_debug0: cpu-debug@22010000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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@ -238,12 +235,14 @@ etm0: etm@22040000 {
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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cluster0_etm0_out_port: endpoint {
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remote-endpoint = <&cluster0_funnel_in_port0>;
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};
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};
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};
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};
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funnel@220c0000 { /* cluster0 funnel */
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compatible = "arm,coresight-funnel", "arm,primecell";
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@ -252,29 +251,28 @@ funnel@220c0000 { /* cluster0 funnel */
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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ports {
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out-ports {
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port {
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cluster0_funnel_out_port: endpoint {
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remote-endpoint = <&main_funnel_in_port0>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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cluster0_funnel_out_port: endpoint {
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remote-endpoint = <&main_funnel_in_port0>;
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};
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};
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port@1 {
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reg = <0>;
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cluster0_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&cluster0_etm0_out_port>;
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};
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};
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port@2 {
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port@1 {
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reg = <1>;
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cluster0_funnel_in_port1: endpoint {
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slave-mode;
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remote-endpoint = <&cluster0_etm1_out_port>;
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};
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};
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@ -297,12 +295,14 @@ etm1: etm@22140000 {
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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cluster0_etm1_out_port: endpoint {
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remote-endpoint = <&cluster0_funnel_in_port1>;
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};
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};
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};
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};
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cpu_debug2: cpu-debug@23010000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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@ -320,12 +320,14 @@ etm2: etm@23040000 {
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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cluster1_etm0_out_port: endpoint {
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remote-endpoint = <&cluster1_funnel_in_port0>;
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};
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};
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};
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};
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funnel@230c0000 { /* cluster1 funnel */
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compatible = "arm,coresight-funnel", "arm,primecell";
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@ -334,43 +336,40 @@ funnel@230c0000 { /* cluster1 funnel */
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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ports {
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out-ports {
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port {
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cluster1_funnel_out_port: endpoint {
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remote-endpoint = <&main_funnel_in_port1>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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cluster1_funnel_out_port: endpoint {
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remote-endpoint = <&main_funnel_in_port1>;
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};
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};
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port@1 {
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reg = <0>;
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cluster1_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&cluster1_etm0_out_port>;
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};
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};
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port@2 {
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port@1 {
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reg = <1>;
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cluster1_funnel_in_port1: endpoint {
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slave-mode;
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remote-endpoint = <&cluster1_etm1_out_port>;
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};
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};
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port@3 {
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port@2 {
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reg = <2>;
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cluster1_funnel_in_port2: endpoint {
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slave-mode;
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remote-endpoint = <&cluster1_etm2_out_port>;
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};
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};
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port@4 {
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port@3 {
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reg = <3>;
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cluster1_funnel_in_port3: endpoint {
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slave-mode;
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remote-endpoint = <&cluster1_etm3_out_port>;
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};
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};
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@ -393,12 +392,14 @@ etm3: etm@23140000 {
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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cluster1_etm1_out_port: endpoint {
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remote-endpoint = <&cluster1_funnel_in_port1>;
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};
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};
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};
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};
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cpu_debug4: cpu-debug@23210000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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@ -416,12 +417,14 @@ etm4: etm@23240000 {
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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cluster1_etm2_out_port: endpoint {
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remote-endpoint = <&cluster1_funnel_in_port2>;
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};
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};
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};
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};
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cpu_debug5: cpu-debug@23310000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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@ -439,12 +442,14 @@ etm5: etm@23340000 {
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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cluster1_etm3_out_port: endpoint {
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remote-endpoint = <&cluster1_funnel_in_port3>;
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};
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};
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};
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};
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replicator@20120000 {
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compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
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@ -454,7 +459,7 @@ replicator@20120000 {
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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ports {
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -472,12 +477,10 @@ replicator_out_port1: endpoint {
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remote-endpoint = <&etr_in_port>;
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};
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};
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/* replicator input port */
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port@2 {
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reg = <0>;
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};
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in-ports {
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port {
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replicator_in_port0: endpoint {
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slave-mode;
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};
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};
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};
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@ -7,23 +7,16 @@ funnel@20130000 { /* cssys1 */
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* output port */
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port@0 {
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reg = <0>;
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out-ports {
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port {
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csys1_funnel_out_port: endpoint {
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remote-endpoint = <&etf1_in_port>;
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};
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};
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/* input port */
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port@1 {
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reg = <0>;
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};
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in-ports {
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port {
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csys1_funnel_in_port0: endpoint {
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slave-mode;
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};
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};
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@ -37,22 +30,15 @@ etf@20140000 { /* etf1 */
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* input port */
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port@0 {
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reg = <0>;
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in-ports {
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port {
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etf1_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&csys1_funnel_out_port>;
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};
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};
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/* output port */
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port@1 {
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reg = <0>;
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};
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out-ports {
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port {
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etf1_out_port: endpoint {
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remote-endpoint = <&csys2_funnel_in_port1>;
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};
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@ -67,20 +53,18 @@ funnel@20150000 { /* cssys2 */
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* output port */
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port@0 {
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reg = <0>;
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out-ports {
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port {
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csys2_funnel_out_port: endpoint {
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remote-endpoint = <&replicator_in_port0>;
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};
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};
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};
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/* input ports */
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port@1 {
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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csys2_funnel_in_port0: endpoint {
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slave-mode;
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@ -88,7 +72,7 @@ csys2_funnel_in_port0: endpoint {
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};
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};
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port@2 {
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port@1 {
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reg = <1>;
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csys2_funnel_in_port1: endpoint {
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slave-mode;
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@ -257,16 +257,13 @@ &stm_out_port {
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remote-endpoint = <&main_funnel_in_port2>;
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};
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&main_funnel {
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ports {
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port@3 {
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&main_funnel_in_ports {
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port@2 {
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reg = <2>;
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main_funnel_in_port2: endpoint {
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slave-mode;
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remote-endpoint = <&stm_out_port>;
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};
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};
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};
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};
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&cpu_debug0 {
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