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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ath10k: Make target cpu address to CE address conversion chip specific
Make the helper converting target virtual address space to CE address space a target type specific to support QCA99X0. Also make this as function instead of macro. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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@ -755,6 +755,26 @@ static void ath10k_pci_rx_replenish_retry(unsigned long ptr)
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ath10k_pci_rx_post(ar);
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}
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static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
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{
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u32 val = 0;
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switch (ar->hw_rev) {
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case ATH10K_HW_QCA988X:
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case ATH10K_HW_QCA6174:
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val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
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CORE_CTRL_ADDRESS) &
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0x7fff) << 21;
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break;
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case ATH10K_HW_QCA99X0:
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val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
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break;
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}
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val |= 0x100000 | (addr & 0xfffff);
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return val;
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}
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/*
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* Diagnostic read/write access is provided for startup/config/debug usage.
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* Caller must guarantee proper alignment, when applicable, and single user
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@ -817,8 +837,7 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
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* convert it from Target CPU virtual address space
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* to CE address space
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*/
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address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
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address);
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address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
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ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
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0);
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@ -976,7 +995,7 @@ static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
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* to
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* CE address space
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*/
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address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
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address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
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remaining_bytes = orig_nbytes;
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ce_data = ce_data_base;
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@ -237,18 +237,6 @@ static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
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#define CDC_WAR_MAGIC_STR 0xceef0000
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#define CDC_WAR_DATA_CE 4
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/*
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* TODO: Should be a function call specific to each Target-type.
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* This convoluted macro converts from Target CPU Virtual Address Space to CE
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* Address Space. As part of this process, we conservatively fetch the current
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* PCIE_BAR. MOST of the time, this should match the upper bits of PCI space
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* for this device; but that's not guaranteed.
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*/
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#define TARG_CPU_SPACE_TO_CE_SPACE(ar, pci_addr, addr) \
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(((ath10k_pci_read32(ar, (SOC_CORE_BASE_ADDRESS | \
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CORE_CTRL_ADDRESS)) & 0x7ff) << 21) | \
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0x100000 | ((addr) & 0xfffff))
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/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
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#define DIAG_ACCESS_CE_TIMEOUT_MS 10
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