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bnx2: Enable auto-mdix when autoneg is disabled.
Auto-mdix currently only works if autoneg is enabled. This patch enables auto-mdix all the time by setting a bit in a PHY register. Define meaningful constants for this PHY registers. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2343,9 +2343,15 @@ bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
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}
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/* ethernet@wirespeed */
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bnx2_write_phy(bp, 0x18, 0x7007);
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bnx2_read_phy(bp, 0x18, &val);
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bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
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bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL);
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bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val);
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val |= AUX_CTL_MISC_CTL_WR | AUX_CTL_MISC_CTL_WIRESPEED;
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/* auto-mdix */
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if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
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val |= AUX_CTL_MISC_CTL_AUTOMDIX;
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bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);
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return 0;
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}
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@ -6471,6 +6471,12 @@ struct l2_fhdr {
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#define BCM5708S_TX_ACTL3 0x17
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#define MII_BNX2_AUX_CTL 0x18
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#define AUX_CTL_MISC_CTL 0x7007
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#define AUX_CTL_MISC_CTL_WIRESPEED (1 << 4)
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#define AUX_CTL_MISC_CTL_AUTOMDIX (1 << 9)
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#define AUX_CTL_MISC_CTL_WR (1 << 15)
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#define MII_BNX2_DSP_RW_PORT 0x15
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#define MII_BNX2_DSP_ADDRESS 0x17
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#define MII_BNX2_DSP_EXPAND_REG 0x0f00
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