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drm/amd/powerplay: update smu function for sienna_cichlid
Add function to check whether baco is support for sienna cichlid. Remove fucntion of get clock by type with latency as it will not be called. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao
Alex Deucher
parent
04af75ef38
commit
40d3b8db83
@ -21,7 +21,6 @@
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*
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*/
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#include "pp_debug.h"
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#include <linux/firmware.h>
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#include <linux/pci.h>
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#include "amdgpu.h"
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@ -36,8 +35,9 @@
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#include "sienna_cichlid_ppt.h"
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#include "smu_v11_0_pptable.h"
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#include "smu_v11_0_7_ppsmc.h"
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#include "nbio/nbio_2_3_offset.h"
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#include "nbio/nbio_2_3_sh_mask.h"
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#include "asic_reg/mp/mp_11_0_sh_mask.h"
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#define FEATURE_MASK(feature) (1ULL << feature)
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@ -516,6 +516,10 @@ static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table
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return -ENOMEM;
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smu_table->metrics_time = 0;
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smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
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if (!smu_table->watermarks_table)
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return -ENOMEM;
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return 0;
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}
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@ -867,40 +871,6 @@ static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
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return ret;
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}
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static int sienna_cichlid_get_clock_by_type_with_latency(struct smu_context *smu,
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enum smu_clk_type clk_type,
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struct pp_clock_levels_with_latency *clocks)
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{
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int ret = 0, i = 0;
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uint32_t level_count = 0, freq = 0;
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switch (clk_type) {
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case SMU_GFXCLK:
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case SMU_DCEFCLK:
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case SMU_SOCCLK:
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ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
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if (ret)
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return ret;
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level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
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clocks->num_levels = level_count;
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for (i = 0; i < level_count; i++) {
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ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
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if (ret)
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return ret;
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clocks->data[i].clocks_in_khz = freq * 1000;
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clocks->data[i].latency_in_us = 0;
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}
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break;
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default:
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break;
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}
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return ret;
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}
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static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
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{
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int ret = 0;
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@ -930,23 +900,13 @@ static int sienna_cichlid_display_config_changed(struct smu_context *smu)
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{
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int ret = 0;
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if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
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!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
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ret = smu_write_watermarks_table(smu);
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if (ret)
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return ret;
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smu->watermarks_bitmap |= WATERMARKS_LOADED;
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}
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if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
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smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
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smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
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/* Sienna_Cichlid do not support to change display num currently */
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ret = 0;
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#if 0
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ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
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smu->display_config->num_display, NULL);
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smu->display_config->num_display,
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NULL);
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#endif
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if (ret)
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return ret;
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@ -1211,8 +1171,6 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
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}
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if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
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if (size < 0)
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return -EINVAL;
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ret = smu_update_table(smu,
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SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
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@ -1338,8 +1296,14 @@ static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
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ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
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if (!ret) {
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if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
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pr_err("Attempt to set divider for DCEFCLK Failed as it not support currently!");
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return ret;
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ret = smu_send_smc_msg_with_param(smu,
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SMU_MSG_SetMinDeepSleepDcefclk,
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min_clocks.dcef_clock_in_sr/100,
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NULL);
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if (ret) {
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pr_err("Attempt to set divider for DCEFCLK Failed!");
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return ret;
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}
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}
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} else {
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pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
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@ -1363,6 +1327,7 @@ static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
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*clock_ranges)
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{
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int i;
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int ret = 0;
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Watermarks_t *table = watermarks;
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if (!table || !clock_ranges)
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@ -1414,6 +1379,17 @@ static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
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clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
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}
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smu->watermarks_bitmap |= WATERMARKS_EXIST;
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if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
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ret = smu_write_watermarks_table(smu);
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if (ret) {
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pr_err("Failed to update WMTABLE!");
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return ret;
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}
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smu->watermarks_bitmap |= WATERMARKS_LOADED;
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}
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return 0;
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}
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@ -1705,8 +1681,10 @@ static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
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pcie_width_cap);
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ret = smu_send_smc_msg_with_param(smu,
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SMU_MSG_OverridePcieParameters,
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smu_pcie_arg, NULL);
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SMU_MSG_OverridePcieParameters,
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smu_pcie_arg,
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NULL);
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if (ret)
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return ret;
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@ -1751,6 +1729,18 @@ int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
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return ret;
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}
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static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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uint32_t val;
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if (!smu_v11_0_baco_is_support(smu))
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return false;
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val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
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return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
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}
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static void sienna_cichlid_dump_pptable(struct smu_context *smu)
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{
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struct smu_table_context *table_context = &smu->smu_table;
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@ -2438,7 +2428,6 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
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.print_clk_levels = sienna_cichlid_print_clk_levels,
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.force_clk_levels = sienna_cichlid_force_clk_levels,
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.populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
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.get_clock_by_type_with_latency = sienna_cichlid_get_clock_by_type_with_latency,
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.pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
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.display_config_changed = sienna_cichlid_display_config_changed,
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.notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
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@ -2500,7 +2489,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
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.register_irq_handler = smu_v11_0_register_irq_handler,
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.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
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.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
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.baco_is_support= smu_v11_0_baco_is_support,
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.baco_is_support= sienna_cichlid_is_baco_supported,
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.baco_get_state = smu_v11_0_baco_get_state,
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.baco_set_state = smu_v11_0_baco_set_state,
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.baco_enter = smu_v11_0_baco_enter,
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