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drm/amdgpu/display: properly guard the calls to swSMU functions
It's only applicable on newer asics. We could end up here when using DC on older asics like SI or KV. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1170 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -106,7 +106,7 @@ bool dm_pp_apply_display_requirements(
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adev->powerplay.pp_funcs->display_configuration_change(
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adev->powerplay.pp_funcs->display_configuration_change(
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adev->powerplay.pp_handle,
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adev->powerplay.pp_handle,
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&adev->pm.pm_display_cfg);
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&adev->pm.pm_display_cfg);
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else
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else if (adev->smu.ppt_funcs)
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smu_display_configuration_change(smu,
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smu_display_configuration_change(smu,
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&adev->pm.pm_display_cfg);
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&adev->pm.pm_display_cfg);
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@ -592,7 +592,7 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
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if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
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if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
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pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
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pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
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&wm_with_clock_ranges);
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&wm_with_clock_ranges);
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else
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else if (adev->smu.ppt_funcs)
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smu_set_watermarks_for_clock_ranges(&adev->smu,
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smu_set_watermarks_for_clock_ranges(&adev->smu,
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&wm_with_clock_ranges);
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&wm_with_clock_ranges);
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}
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}
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