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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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x86: fix IO write barrier
wmb() on x86 must always include a barrier, because stores can go out of order in many cases when dealing with devices (eg. WC memory). Signed-off-by: Nick Piggin <npiggin@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -216,6 +216,7 @@ static inline unsigned long get_limit(unsigned long segment)
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#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
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#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
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#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
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/**
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* read_barrier_depends - Flush all pending reads that subsequents reads
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@ -271,18 +272,14 @@ static inline unsigned long get_limit(unsigned long segment)
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#define read_barrier_depends() do { } while(0)
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#ifdef CONFIG_X86_OOSTORE
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/* Actually there are no OOO store capable CPUs for now that do SSE,
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but make it already an possibility. */
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#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
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#else
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#define wmb() __asm__ __volatile__ ("": : :"memory")
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#endif
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#ifdef CONFIG_X86_OOSTORE
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# define smp_wmb() wmb()
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#else
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# define smp_wmb() barrier()
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#endif
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#define smp_read_barrier_depends() read_barrier_depends()
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#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
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#else
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@ -159,12 +159,8 @@ static inline void write_cr8(unsigned long val)
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*/
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#ifdef CONFIG_UNORDERED_IO
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#define wmb() asm volatile("sfence" ::: "memory")
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#else
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#define wmb() asm volatile("" ::: "memory")
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#endif
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#define read_barrier_depends() do {} while(0)
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#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
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