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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 05:56:46 +07:00
x86: intel.c put workaround for old cpus together
consolidate the code some more. No change in functionality intended. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Yinghai Lu
Ingo Molnar
parent
879d792b66
commit
4052704d92
@ -63,28 +63,6 @@ int __cpuinit ppro_with_ram_bug(void)
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return 0;
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}
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/*
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* P4 Xeon errata 037 workaround.
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* Hardware prefetcher may cause stale data to be loaded into the cache.
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*/
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static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
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{
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unsigned long lo, hi;
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if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
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rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
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if ((lo & (1<<9)) == 0) {
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printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
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printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
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lo |= (1<<9); /* Disable hw prefetching */
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wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
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}
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}
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}
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#ifdef CONFIG_X86_F00F_BUG
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static void __cpuinit trap_init_f00f_bug(void)
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{
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@ -98,6 +76,88 @@ static void __cpuinit trap_init_f00f_bug(void)
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load_idt(&idt_descr);
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}
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#endif
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static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
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{
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unsigned long lo, hi;
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#ifdef CONFIG_X86_F00F_BUG
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/*
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* All current models of Pentium and Pentium with MMX technology CPUs
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* have the F0 0F bug, which lets nonprivileged users lock up the system.
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* Note that the workaround only should be initialized once...
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*/
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c->f00f_bug = 0;
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if (!paravirt_enabled() && c->x86 == 5) {
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static int f00f_workaround_enabled;
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c->f00f_bug = 1;
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if (!f00f_workaround_enabled) {
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trap_init_f00f_bug();
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printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
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f00f_workaround_enabled = 1;
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}
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}
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#endif
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/*
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* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
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* model 3 mask 3
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*/
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if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
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clear_cpu_cap(c, X86_FEATURE_SEP);
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/*
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* P4 Xeon errata 037 workaround.
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* Hardware prefetcher may cause stale data to be loaded into the cache.
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*/
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if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
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rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
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if ((lo & (1<<9)) == 0) {
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printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
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printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
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lo |= (1<<9); /* Disable hw prefetching */
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wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
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}
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}
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/*
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* See if we have a good local APIC by checking for buggy Pentia,
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* i.e. all B steppings and the C2 stepping of P54C when using their
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* integrated APIC (see 11AP erratum in "Pentium Processor
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* Specification Update").
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*/
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if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
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(c->x86_mask < 0x6 || c->x86_mask == 0xb))
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set_cpu_cap(c, X86_FEATURE_11AP);
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#ifdef CONFIG_X86_INTEL_USERCOPY
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/*
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* Set up the preferred alignment for movsl bulk memory moves
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*/
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switch (c->x86) {
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case 4: /* 486: untested */
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break;
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case 5: /* Old Pentia: untested */
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break;
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case 6: /* PII/PIII only like movsl with 8-byte alignment */
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movsl_mask.mask = 7;
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break;
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case 15: /* P4 is OK down to 8-byte alignment */
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movsl_mask.mask = 7;
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break;
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}
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#endif
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#ifdef CONFIG_X86_NUMAQ
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numaq_tsc_disable();
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#endif
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}
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#else
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static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
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{
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}
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#endif
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static void __cpuinit srat_detect_node(void)
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@ -139,28 +199,10 @@ static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
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static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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{
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unsigned int l2 = 0;
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char *p = NULL;
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early_init_intel(c);
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#ifdef CONFIG_X86_F00F_BUG
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/*
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* All current models of Pentium and Pentium with MMX technology CPUs
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* have the F0 0F bug, which lets nonprivileged users lock up the system.
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* Note that the workaround only should be initialized once...
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*/
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c->f00f_bug = 0;
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if (!paravirt_enabled() && c->x86 == 5) {
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static int f00f_workaround_enabled;
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c->f00f_bug = 1;
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if (!f00f_workaround_enabled) {
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trap_init_f00f_bug();
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printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
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f00f_workaround_enabled = 1;
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}
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}
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#endif
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intel_workarounds(c);
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l2 = init_intel_cacheinfo(c);
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if (c->cpuid_level > 9) {
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@ -170,17 +212,32 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
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}
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#ifdef CONFIG_X86_32
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/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
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if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
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clear_cpu_cap(c, X86_FEATURE_SEP);
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if (cpu_has_xmm2)
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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if (cpu_has_ds) {
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unsigned int l1;
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rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
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if (!(l1 & (1<<11)))
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set_cpu_cap(c, X86_FEATURE_BTS);
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if (!(l1 & (1<<12)))
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set_cpu_cap(c, X86_FEATURE_PEBS);
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ds_init_intel(c);
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}
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#ifdef CONFIG_X86_64
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if (c->x86 == 15)
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c->x86_cache_alignment = c->x86_clflush_size * 2;
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if (c->x86 == 6)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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#else
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/*
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* Names for the Pentium II/Celeron processors
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* detectable only by also checking the cache size.
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* Dixon is NOT a Celeron.
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*/
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if (c->x86 == 6) {
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char *p = NULL;
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switch (c->x86_model) {
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case 5:
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if (c->x86_mask == 0) {
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@ -203,51 +260,11 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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p = "Celeron (Coppermine)";
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break;
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}
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if (p)
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strcpy(c->x86_model_id, p);
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}
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if (p)
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strcpy(c->x86_model_id, p);
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Intel_errata_workarounds(c);
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#ifdef CONFIG_X86_INTEL_USERCOPY
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/*
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* Set up the preferred alignment for movsl bulk memory moves
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*/
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switch (c->x86) {
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case 4: /* 486: untested */
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break;
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case 5: /* Old Pentia: untested */
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break;
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case 6: /* PII/PIII only like movsl with 8-byte alignment */
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movsl_mask.mask = 7;
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break;
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case 15: /* P4 is OK down to 8-byte alignment */
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movsl_mask.mask = 7;
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break;
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}
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#endif
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#endif
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if (cpu_has_xmm2)
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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if (cpu_has_ds) {
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unsigned int l1;
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rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
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if (!(l1 & (1<<11)))
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set_cpu_cap(c, X86_FEATURE_BTS);
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if (!(l1 & (1<<12)))
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set_cpu_cap(c, X86_FEATURE_PEBS);
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ds_init_intel(c);
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}
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#ifdef CONFIG_X86_64
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if (c->x86 == 15)
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c->x86_cache_alignment = c->x86_clflush_size * 2;
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if (c->x86 == 6)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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#else
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if (c->x86 == 15)
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set_cpu_cap(c, X86_FEATURE_P4);
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if (c->x86 == 6)
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@ -256,19 +273,6 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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if (cpu_has_bts)
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ptrace_bts_init_intel(c);
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/*
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* See if we have a good local APIC by checking for buggy Pentia,
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* i.e. all B steppings and the C2 stepping of P54C when using their
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* integrated APIC (see 11AP erratum in "Pentium Processor
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* Specification Update").
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*/
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if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
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(c->x86_mask < 0x6 || c->x86_mask == 0xb))
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set_cpu_cap(c, X86_FEATURE_11AP);
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#ifdef CONFIG_X86_NUMAQ
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numaq_tsc_disable();
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#endif
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#endif
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detect_extended_topology(c);
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