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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'fbdev-for-linus' of git://github.com/schandinat/linux-2.6
* 'fbdev-for-linus' of git://github.com/schandinat/linux-2.6: viafb: correct sync polarity for OLPC DCON video:da8xx-fb: Disable and reset sequence on version2 of LCDC OMAPDSS: DISPC: skip scaling calculations when not scaling OMAPFB: fix compilation warnings due to missing include OMAPDSS: HDMI: fix returned HDMI pixel clock
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401d0069cb
@ -116,6 +116,7 @@
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/* Clock registers available only on Version 2 */
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#define LCD_CLK_ENABLE_REG 0x6c
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#define LCD_CLK_RESET_REG 0x70
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#define LCD_CLK_MAIN_RESET BIT(3)
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#define LCD_NUM_BUFFERS 2
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@ -244,6 +245,10 @@ static inline void lcd_enable_raster(void)
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{
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u32 reg;
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/* Bring LCDC out of reset */
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if (lcd_revision == LCD_VERSION_2)
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lcdc_write(0, LCD_CLK_RESET_REG);
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reg = lcdc_read(LCD_RASTER_CTRL_REG);
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if (!(reg & LCD_RASTER_ENABLE))
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lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
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@ -257,6 +262,10 @@ static inline void lcd_disable_raster(void)
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reg = lcdc_read(LCD_RASTER_CTRL_REG);
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if (reg & LCD_RASTER_ENABLE)
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lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
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if (lcd_revision == LCD_VERSION_2)
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/* Write 1 to reset LCDC */
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lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
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}
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static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
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@ -584,8 +593,12 @@ static void lcd_reset(struct da8xx_fb_par *par)
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lcdc_write(0, LCD_DMA_CTRL_REG);
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lcdc_write(0, LCD_RASTER_CTRL_REG);
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if (lcd_revision == LCD_VERSION_2)
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if (lcd_revision == LCD_VERSION_2) {
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lcdc_write(0, LCD_INT_ENABLE_SET_REG);
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/* Write 1 to reset */
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lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
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lcdc_write(0, LCD_CLK_RESET_REG);
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}
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}
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static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
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@ -19,6 +19,7 @@
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/mm.h>
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#include <linux/vmalloc.h>
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@ -1720,12 +1720,11 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
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const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
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unsigned long fclk = 0;
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if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
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if (width != out_width || height != out_height)
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return -EINVAL;
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else
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return 0;
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}
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if (width == out_width && height == out_height)
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return 0;
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if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
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return -EINVAL;
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if (out_width < width / maxdownscale ||
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out_width > width * 8)
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@ -269,7 +269,7 @@ static void update_hdmi_timings(struct hdmi_config *cfg,
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unsigned long hdmi_get_pixel_clock(void)
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{
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/* HDMI Pixel Clock in Mhz */
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return hdmi.ip_data.cfg.timings.timings.pixel_clock * 10000;
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return hdmi.ip_data.cfg.timings.timings.pixel_clock * 1000;
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}
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static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
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@ -559,8 +559,8 @@
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#define M1200X720_R60_VSP POSITIVE
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/* 1200x900@60 Sync Polarity (DCON) */
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#define M1200X900_R60_HSP NEGATIVE
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#define M1200X900_R60_VSP NEGATIVE
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#define M1200X900_R60_HSP POSITIVE
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#define M1200X900_R60_VSP POSITIVE
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/* 1280x600@60 Sync Polarity (GTF Mode) */
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#define M1280x600_R60_HSP NEGATIVE
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