ARM64: dts: marvell: add NAND support on the CP110

The NAND controller used in A7K/A8K is present on the CP110. It is
compatible with the pxa-nand driver.

However, due to the limiation of the pins available this controller is
only usable on the CPM for A7K and on the CPS for A8K.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit is contained in:
Gregory CLEMENT 2017-08-04 17:32:32 +02:00
parent 9be778f6c6
commit 40118824c5
2 changed files with 30 additions and 0 deletions

View File

@ -249,6 +249,21 @@ cpm_i2c1: i2c@701100 {
status = "disabled";
};
cpm_nand: nand@720000 {
/*
* Due to the limiation of the pin available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
compatible = "marvell,armada370-nand";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 2>;
status = "disabled";
};
cpm_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;

View File

@ -250,6 +250,21 @@ cps_i2c1: i2c@701100 {
status = "disabled";
};
cps_nand: nand@720000 {
/*
* Due to the limiation of the pin available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
compatible = "marvell,armada370-nand";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 2>;
status = "disabled";
};
cps_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;