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ARM: dts: r8a7793: Add SCIF fallback compatibility strings

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Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2016-01-29 10:32:06 +01:00 committed by Simon Horman
parent b5b52dd7d0
commit 3ffc90a3e9
1 changed files with 36 additions and 18 deletions
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54
arch/arm/boot/dts/r8a7793.dtsi
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@ -479,7 +479,8 @@ pfc: pfc@e6060000 {
};
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7793", "renesas,scifa";
compatible = "renesas,scifa-r8a7793",
"renesas,rcar-gen2-scifa", "renesas,scifa";
reg = <0 0xe6c40000 0 64>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
@ -491,7 +492,8 @@ scifa0: serial@e6c40000 {
};
scifa1: serial@e6c50000 {
compatible = "renesas,scifa-r8a7793", "renesas,scifa";
compatible = "renesas,scifa-r8a7793",
"renesas,rcar-gen2-scifa", "renesas,scifa";
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
@ -503,7 +505,8 @@ scifa1: serial@e6c50000 {
};
scifa2: serial@e6c60000 {
compatible = "renesas,scifa-r8a7793", "renesas,scifa";
compatible = "renesas,scifa-r8a7793",
"renesas,rcar-gen2-scifa", "renesas,scifa";
reg = <0 0xe6c60000 0 64>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
@ -515,7 +518,8 @@ scifa2: serial@e6c60000 {
};
scifa3: serial@e6c70000 {
compatible = "renesas,scifa-r8a7793", "renesas,scifa";
compatible = "renesas,scifa-r8a7793",
"renesas,rcar-gen2-scifa", "renesas,scifa";
reg = <0 0xe6c70000 0 64>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
@ -527,7 +531,8 @@ scifa3: serial@e6c70000 {
};
scifa4: serial@e6c78000 {
compatible = "renesas,scifa-r8a7793", "renesas,scifa";
compatible = "renesas,scifa-r8a7793",
"renesas,rcar-gen2-scifa", "renesas,scifa";
reg = <0 0xe6c78000 0 64>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
@ -539,7 +544,8 @@ scifa4: serial@e6c78000 {
};
scifa5: serial@e6c80000 {
compatible = "renesas,scifa-r8a7793", "renesas,scifa";
compatible = "renesas,scifa-r8a7793",
"renesas,rcar-gen2-scifa", "renesas,scifa";
reg = <0 0xe6c80000 0 64>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
@ -551,7 +557,8 @@ scifa5: serial@e6c80000 {
};
scifb0: serial@e6c20000 {
compatible = "renesas,scifb-r8a7793", "renesas,scifb";
compatible = "renesas,scifb-r8a7793",
"renesas,rcar-gen2-scifb", "renesas,scifb";
reg = <0 0xe6c20000 0 64>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
@ -563,7 +570,8 @@ scifb0: serial@e6c20000 {
};
scifb1: serial@e6c30000 {
compatible = "renesas,scifb-r8a7793", "renesas,scifb";
compatible = "renesas,scifb-r8a7793",
"renesas,rcar-gen2-scifb", "renesas,scifb";
reg = <0 0xe6c30000 0 64>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
@ -575,7 +583,8 @@ scifb1: serial@e6c30000 {
};
scifb2: serial@e6ce0000 {
compatible = "renesas,scifb-r8a7793", "renesas,scifb";
compatible = "renesas,scifb-r8a7793",
"renesas,rcar-gen2-scifb", "renesas,scifb";
reg = <0 0xe6ce0000 0 64>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
@ -587,7 +596,8 @@ scifb2: serial@e6ce0000 {
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a7793", "renesas,scif";
compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
"renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
@ -599,7 +609,8 @@ scif0: serial@e6e60000 {
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a7793", "renesas,scif";
compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
"renesas,scif";
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
@ -611,7 +622,8 @@ scif1: serial@e6e68000 {
};
scif2: serial@e6e58000 {
compatible = "renesas,scif-r8a7793", "renesas,scif";
compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
"renesas,scif";
reg = <0 0xe6e58000 0 64>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF2>;
@ -623,7 +635,8 @@ scif2: serial@e6e58000 {
};
scif3: serial@e6ea8000 {
compatible = "renesas,scif-r8a7793", "renesas,scif";
compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
"renesas,scif";
reg = <0 0xe6ea8000 0 64>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF3>;
@ -635,7 +648,8 @@ scif3: serial@e6ea8000 {
};
scif4: serial@e6ee0000 {
compatible = "renesas,scif-r8a7793", "renesas,scif";
compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
"renesas,scif";
reg = <0 0xe6ee0000 0 64>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF4>;
@ -647,7 +661,8 @@ scif4: serial@e6ee0000 {
};
scif5: serial@e6ee8000 {
compatible = "renesas,scif-r8a7793", "renesas,scif";
compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
"renesas,scif";
reg = <0 0xe6ee8000 0 64>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF5>;
@ -659,7 +674,8 @@ scif5: serial@e6ee8000 {
};
hscif0: serial@e62c0000 {
compatible = "renesas,hscif-r8a7793", "renesas,hscif";
compatible = "renesas,hscif-r8a7793",
"renesas,rcar-gen2-hscif", "renesas,hscif";
reg = <0 0xe62c0000 0 96>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>;
@ -671,7 +687,8 @@ hscif0: serial@e62c0000 {
};
hscif1: serial@e62c8000 {
compatible = "renesas,hscif-r8a7793", "renesas,hscif";
compatible = "renesas,hscif-r8a7793",
"renesas,rcar-gen2-hscif", "renesas,hscif";
reg = <0 0xe62c8000 0 96>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>;
@ -683,7 +700,8 @@ hscif1: serial@e62c8000 {
};
hscif2: serial@e62d0000 {
compatible = "renesas,hscif-r8a7793", "renesas,hscif";
compatible = "renesas,hscif-r8a7793",
"renesas,rcar-gen2-hscif", "renesas,hscif";
reg = <0 0xe62d0000 0 96>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>;