From 3f7f3b0fb4563947424673d9b6786f46111462d9 Mon Sep 17 00:00:00 2001 From: Shunqian Zheng Date: Mon, 12 Mar 2018 09:50:48 +0800 Subject: [PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO on rk3399 The ACLK_VIO is a parent clock used by a several children, its suggested clock rate is 400MHz. Right now it gets 400MHz because it sources from CPLL(800M) and divides by 2 after reset. It's good not to rely on default values like this, so let's explicitly set it. NOTE: it's expected that at least one board may override cru node and set the CPLL to 1.6 GHz. On that board it will be very important to be explicit about aclk-vio being 400 MHz. Signed-off-by: Shunqian Zheng Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 6 ++++-- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 6e50768a34ce..300f11daf1ae 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -586,7 +586,8 @@ &cru { <&cru PCLK_PERIHP>, <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, - <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>; assigned-clock-rates = <600000000>, <800000000>, <1000000000>, @@ -594,7 +595,8 @@ &cru { <37500000>, <100000000>, <100000000>, <50000000>, <800000000>, - <100000000>, <50000000>; + <100000000>, <50000000>, + <400000000>; }; &emmc_phy { diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 65a42eee01de..a8340d94396e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1322,7 +1322,8 @@ cru: clock-controller@ff760000 { <&cru PCLK_PERIHP>, <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, - <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>; assigned-clock-rates = <594000000>, <800000000>, <1000000000>, @@ -1330,7 +1331,8 @@ cru: clock-controller@ff760000 { <37500000>, <100000000>, <100000000>, <50000000>, <600000000>, - <100000000>, <50000000>; + <100000000>, <50000000>, + <400000000>; }; grf: syscon@ff770000 {