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drm/amdgpu/mes10.1: add the mes fw api
Add the definitions of mes commands. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jack Xiao
Alex Deucher
parent
e25c0dcd0d
commit
3f63345d38
405
drivers/gpu/drm/amd/amdgpu/mes_api_def.h
Normal file
405
drivers/gpu/drm/amd/amdgpu/mes_api_def.h
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __MES_API_DEF_H__
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#define __MES_API_DEF_H__
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#pragma pack(push, 4)
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typedef uint32_t uint32;
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typedef uint64_t uint64;
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#define MES_API_VERSION 1
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//Driver submits one API(cmd) as a single Frame and this command size is same for all API
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//to ease the debugging and parsing of ring buffer.
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enum {API_FRAME_SIZE_IN_DWORDS = 64};
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//To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in,
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//this creates another queue
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enum {API_NUMBER_OF_COMMAND_MAX = 32};
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enum MES_API_TYPE
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{
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MES_API_TYPE_SCHEDULER = 1,
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MES_API_TYPE_MAX
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};
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enum MES_SCH_API_OPCODE
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{
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MES_SCH_API_SET_HW_RSRC = 0,
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MES_SCH_API_SET_SCHEDULING_CONFIG = 1, //agreegated db, quantums, etc
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MES_SCH_API_ADD_QUEUE = 2,
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MES_SCH_API_REMOVE_QUEUE = 3,
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MES_SCH_API_PERFORM_YIELD = 4,
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MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, //For windows GANG = Context
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MES_SCH_API_SUSPEND = 6,
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MES_SCH_API_RESUME = 7,
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MES_SCH_API_RESET = 8,
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MES_SCH_API_SET_LOG_BUFFER = 9,
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MES_SCH_API_CHANGE_GANG_PRORITY = 10,
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MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
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MES_SCH_API_PROGRAM_GDS = 12,
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MES_SCH_API_MAX = 0xFF
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};
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union MES_API_HEADER
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{
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struct
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{
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uint32 type : 4; // 0 - Invalid; 1 - Scheduling; 2 - TBD
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uint32 opcode : 8;
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uint32 dwsize : 8; //including header
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uint32 reserved : 12;
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};
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uint32 u32All;
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};
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enum MES_AMD_PRIORITY_LEVEL
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{
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AMD_PRIORITY_LEVEL_LOW = 0,
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AMD_PRIORITY_LEVEL_NORMAL = 1,
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AMD_PRIORITY_LEVEL_MEDIUM = 2,
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AMD_PRIORITY_LEVEL_HIGH = 3,
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AMD_PRIORITY_LEVEL_REALTIME = 4,
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AMD_PRIORITY_NUM_LEVELS
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};
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enum MES_QUEUE_TYPE
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{
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MES_QUEUE_TYPE_GFX,
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MES_QUEUE_TYPE_COMPUTE,
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MES_QUEUE_TYPE_SDMA,
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MES_QUEUE_TYPE_MAX,
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};
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struct MES_API_STATUS
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{
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uint64 api_completion_fence_addr;
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uint64 api_completion_fence_value;
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};
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enum { MAX_COMPUTE_PIPES = 8 };
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enum { MAX_GFX_PIPES = 2 };
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enum { MAX_SDMA_PIPES = 2 };
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enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
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enum { MAX_GFX_HQD_PER_PIPE = 8 };
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enum { MAX_SDMA_HQD_PER_PIPE = 10 };
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enum { MAX_QUEUES_IN_A_GANG = 8 };
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enum VM_HUB_TYPE
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{
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VM_HUB_TYPE_GC = 0,
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VM_HUB_TYPE_MM = 1,
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VM_HUB_TYPE_MAX,
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};
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enum { VMID_INVALID = 0xffff };
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enum { MAX_VMID_GCHUB = 16 };
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enum { MAX_VMID_MMHUB = 16 };
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enum MES_LOG_OPERATION
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{
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MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0
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};
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enum MES_LOG_CONTEXT_STATE
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{
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MES_LOG_CONTEXT_STATE_IDLE = 0,
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MES_LOG_CONTEXT_STATE_RUNNING = 1,
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MES_LOG_CONTEXT_STATE_READY = 2,
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MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
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};
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struct MES_LOG_CONTEXT_STATE_CHANGE
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{
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void* h_context;
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enum MES_LOG_CONTEXT_STATE new_context_state;
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};
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struct MES_LOG_ENTRY_HEADER
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{
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uint32 first_free_entry_index;
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uint32 wraparound_count;
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uint64 number_of_entries;
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uint64 reserved[2];
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};
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struct MES_LOG_ENTRY_DATA
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{
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uint64 gpu_time_stamp;
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uint32 operation_type; //operation_type is of MES_LOG_OPERATION type
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uint32 reserved_operation_type_bits;
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union
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{
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struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
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uint64 reserved_operation_data[2];
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};
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};
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struct MES_LOG_BUFFER
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{
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struct MES_LOG_ENTRY_HEADER header;
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struct MES_LOG_ENTRY_DATA entries[1];
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};
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union MESAPI_SET_HW_RESOURCES
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{
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struct
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{
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union MES_API_HEADER header;
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uint32 vmid_mask_mmhub;
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uint32 vmid_mask_gfxhub;
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uint32 gds_size;
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uint32 paging_vmid;
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uint32 compute_hqd_mask[MAX_COMPUTE_PIPES];
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uint32 gfx_hqd_mask[MAX_GFX_PIPES];
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uint32 sdma_hqd_mask[MAX_SDMA_PIPES];
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uint32 agreegated_doorbells[AMD_PRIORITY_NUM_LEVELS];
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uint64 g_sch_ctx_gpu_mc_ptr;
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struct MES_API_STATUS api_status;
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};
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uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__ADD_QUEUE
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{
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struct
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{
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union MES_API_HEADER header;
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uint32 process_id;
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uint64 page_table_base_addr;
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uint64 process_va_start;
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uint64 process_va_end;
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uint64 process_quantum;
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uint64 process_context_addr;
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uint64 gang_quantum;
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uint64 gang_context_addr;
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uint32 inprocess_gang_priority;
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enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
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uint32 doorbell_offset;
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uint64 mqd_addr;
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uint64 wptr_addr;
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enum MES_QUEUE_TYPE queue_type;
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uint32 gds_base;
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uint32 gds_size;
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uint32 gws_base;
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uint32 gws_size;
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uint32 oa_mask;
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struct
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{
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uint32 paging : 1;
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uint32 program_gds : 1;
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uint32 reserved : 30;
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};
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struct MES_API_STATUS api_status;
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};
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uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__REMOVE_QUEUE
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{
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struct
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{
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union MES_API_HEADER header;
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uint32 doorbell_offset;
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uint64 gang_context_addr;
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struct MES_API_STATUS api_status;
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};
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uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__SET_SCHEDULING_CONFIG
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{
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struct
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{
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union MES_API_HEADER header;
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// Grace period when preempting another priority band for this priority band.
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// The value for idle priority band is ignored, as it never preempts other bands.
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uint64 grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
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// Default quantum for scheduling across processes within a priority band.
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uint64 process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
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// Default grace period for processes that preempt each other within a priority band.
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uint64 process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
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// For normal level this field specifies the target GPU percentage in situations when it's starved by the high level.
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// Valid values are between 0 and 50, with the default being 10.
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uint32 normal_yield_percent;
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struct MES_API_STATUS api_status;
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};
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uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__PERFORM_YIELD
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{
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struct
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{
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union MES_API_HEADER header;
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uint32 dummy;
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struct MES_API_STATUS api_status;
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};
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uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__CHANGE_GANG_PRIORITY_LEVEL
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{
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struct
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{
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union MES_API_HEADER header;
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uint32 inprocess_gang_priority;
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enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
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uint64 gang_quantum;
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uint64 gang_context_addr;
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struct MES_API_STATUS api_status;
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};
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uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__SUSPEND
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{
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struct
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{
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union MES_API_HEADER header;
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//false - suspend all gangs; true - specific gang
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struct
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{
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uint32 suspend_all_gangs : 1;
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uint32 reserved : 31;
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};
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//gang_context_addr is valid only if suspend_all = false
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uint64 gang_context_addr;
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uint64 suspend_fence_addr;
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uint32 suspend_fence_value;
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struct MES_API_STATUS api_status;
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};
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uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__RESUME
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{
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struct
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{
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union MES_API_HEADER header;
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//false - resume all gangs; true - specified gang
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struct
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{
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uint32 resume_all_gangs : 1;
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uint32 reserved : 31;
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};
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//valid only if resume_all_gangs = false
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uint64 gang_context_addr;
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struct MES_API_STATUS api_status;
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};
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uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__RESET
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{
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struct
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{
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union MES_API_HEADER header;
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struct
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{
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uint32 reset_queue : 1;
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uint32 reserved : 31;
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};
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uint64 gang_context_addr;
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uint32 doorbell_offset; //valid only if reset_queue = true
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struct MES_API_STATUS api_status;
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};
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uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__SET_LOGGING_BUFFER
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{
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struct
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{
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union MES_API_HEADER header;
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//There are separate log buffers for each queue type
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enum MES_QUEUE_TYPE log_type;
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//Log buffer GPU Address
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uint64 logging_buffer_addr;
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//number of entries in the log buffer
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uint32 number_of_entries;
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//Entry index at which CPU interrupt needs to be signalled
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uint32 interrupt_entry;
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struct MES_API_STATUS api_status;
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};
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uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__QUERY_MES_STATUS
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{
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struct
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{
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union MES_API_HEADER header;
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bool mes_healthy; //0 - not healthy, 1 - healthy
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struct MES_API_STATUS api_status;
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};
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uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__PROGRAM_GDS
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{
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struct
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{
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union MES_API_HEADER header;
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uint64 process_context_addr;
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uint32 gds_base;
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uint32 gds_size;
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uint32 gws_base;
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uint32 gws_size;
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uint32 oa_mask;
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struct MES_API_STATUS api_status;
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};
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uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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#pragma pack(pop)
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#endif
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@ -29,6 +29,7 @@
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#include "gc/gc_10_1_0_offset.h"
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#include "gc/gc_10_1_0_sh_mask.h"
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#include "v10_structs.h"
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#include "mes_api_def.h"
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MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
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