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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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PCI: dwc: Remove old MSI IRQs API
Remove the unused old MSI IRQs API from pcie-designware based on struct msi_controller that should now be considered obsolete. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Niklas Cassel <niklas.cassel@axis.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Gustavo Pimentel
Lorenzo Pieralisi
parent
7c5925afbc
commit
3f43ccc4ea
@ -157,7 +157,7 @@ void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
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BIT(bit_pos));
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}
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int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
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int ks_dw_pcie_msi_host_init(struct pcie_port *pp)
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{
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return dw_pcie_allocate_domains(pp);
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}
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@ -53,6 +53,5 @@ void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp);
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void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
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void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
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void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
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int ks_dw_pcie_msi_host_init(struct pcie_port *pp,
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struct msi_controller *chip);
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int ks_dw_pcie_msi_host_init(struct pcie_port *pp);
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int ks_dw_pcie_link_up(struct dw_pcie *pci);
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@ -182,8 +182,7 @@ static int ls1021_pcie_host_init(struct pcie_port *pp)
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return ls_pcie_host_init(pp);
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}
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static int ls_pcie_msi_host_init(struct pcie_port *pp,
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struct msi_controller *chip)
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static int ls_pcie_msi_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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@ -43,14 +43,6 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
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return dw_pcie_write(pci->dbi_base + where, size, val);
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}
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static struct irq_chip dw_msi_irq_chip = {
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.name = "PCI-MSI",
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.irq_enable = pci_msi_unmask_irq,
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.irq_disable = pci_msi_mask_irq,
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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};
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static void dw_msi_ack_irq(struct irq_data *d)
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{
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irq_chip_ack_parent(d);
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@ -320,186 +312,6 @@ void dw_pcie_msi_init(struct pcie_port *pp)
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upper_32_bits(msi_target));
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}
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static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
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{
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unsigned int res, bit, ctrl;
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ctrl = irq / 32;
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res = ctrl * 12;
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bit = irq % 32;
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pp->irq_status[ctrl] &= ~(1 << bit);
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
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pp->irq_status[ctrl]);
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}
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static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
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unsigned int nvec, unsigned int pos)
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{
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unsigned int i;
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for (i = 0; i < nvec; i++) {
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irq_set_msi_desc_off(irq_base, i, NULL);
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/* Disable corresponding interrupt on MSI controller */
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if (pp->ops->msi_clear_irq)
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pp->ops->msi_clear_irq(pp, pos + i);
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else
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dw_pcie_msi_clear_irq(pp, pos + i);
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}
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bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
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}
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static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
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{
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unsigned int res, bit, ctrl;
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ctrl = irq / 32;
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res = ctrl * 12;
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bit = irq % 32;
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pp->irq_status[ctrl] |= 1 << bit;
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
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pp->irq_status[ctrl]);
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}
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static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
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{
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int irq, pos0, i;
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struct pcie_port *pp;
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pp = (struct pcie_port *)msi_desc_to_pci_sysdata(desc);
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pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
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order_base_2(no_irqs));
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if (pos0 < 0)
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goto no_valid_irq;
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irq = irq_find_mapping(pp->irq_domain, pos0);
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if (!irq)
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goto no_valid_irq;
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/*
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* irq_create_mapping (called from dw_pcie_host_init) pre-allocates
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* descs so there is no need to allocate descs here. We can therefore
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* assume that if irq_find_mapping above returns non-zero, then the
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* descs are also successfully allocated.
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*/
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for (i = 0; i < no_irqs; i++) {
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if (irq_set_msi_desc_off(irq, i, desc) != 0) {
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clear_irq_range(pp, irq, i, pos0);
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goto no_valid_irq;
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}
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/*Enable corresponding interrupt in MSI interrupt controller */
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if (pp->ops->msi_set_irq)
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pp->ops->msi_set_irq(pp, pos0 + i);
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else
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dw_pcie_msi_set_irq(pp, pos0 + i);
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}
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*pos = pos0;
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desc->nvec_used = no_irqs;
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desc->msi_attrib.multiple = order_base_2(no_irqs);
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return irq;
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no_valid_irq:
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*pos = pos0;
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return -ENOSPC;
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}
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static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
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{
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struct msi_msg msg;
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u64 msi_target;
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if (pp->ops->get_msi_addr)
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msi_target = pp->ops->get_msi_addr(pp);
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else
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msi_target = (u64)pp->msi_data;
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msg.address_lo = (u32)(msi_target & 0xffffffff);
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msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
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if (pp->ops->get_msi_data)
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msg.data = pp->ops->get_msi_data(pp, pos);
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else
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msg.data = pos;
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pci_write_msi_msg(irq, &msg);
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}
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static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
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struct msi_desc *desc)
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{
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int irq, pos;
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struct pcie_port *pp = pdev->bus->sysdata;
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if (desc->msi_attrib.is_msix)
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return -EINVAL;
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irq = assign_irq(1, desc, &pos);
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if (irq < 0)
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return irq;
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dw_msi_setup_msg(pp, irq, pos);
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return 0;
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}
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static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
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int nvec, int type)
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{
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#ifdef CONFIG_PCI_MSI
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int irq, pos;
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struct msi_desc *desc;
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struct pcie_port *pp = pdev->bus->sysdata;
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/* MSI-X interrupts are not supported */
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if (type == PCI_CAP_ID_MSIX)
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return -EINVAL;
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WARN_ON(!list_is_singular(&pdev->dev.msi_list));
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desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
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irq = assign_irq(nvec, desc, &pos);
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if (irq < 0)
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return irq;
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dw_msi_setup_msg(pp, irq, pos);
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return 0;
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#else
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return -EINVAL;
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#endif
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}
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static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
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{
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struct irq_data *data = irq_get_irq_data(irq);
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struct msi_desc *msi = irq_data_get_msi_desc(data);
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struct pcie_port *pp = (struct pcie_port *)msi_desc_to_pci_sysdata(msi);
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clear_irq_range(pp, irq, 1, data->hwirq);
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}
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static struct msi_controller dw_pcie_msi_chip = {
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.setup_irq = dw_msi_setup_irq,
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.setup_irqs = dw_msi_setup_irqs,
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.teardown_irq = dw_msi_teardown_irq,
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};
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static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops msi_domain_ops = {
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.map = dw_pcie_msi_map,
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};
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int dw_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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@ -639,7 +451,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
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dw_chained_msi_isr,
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pp);
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} else {
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ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
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ret = pp->ops->msi_host_init(pp);
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if (ret < 0)
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goto error;
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}
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@ -151,7 +151,7 @@ struct dw_pcie_host_ops {
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u32 (*get_msi_data)(struct pcie_port *pp, int pos);
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void (*scan_bus)(struct pcie_port *pp);
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void (*set_num_vectors)(struct pcie_port *pp);
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int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
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int (*msi_host_init)(struct pcie_port *pp);
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void (*msi_irq_ack)(int irq, struct pcie_port *pp);
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};
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