Reset controller changes for v4.6

- add support for the imgtec Pistachio SoC reset controller
 - make struct reset_control_ops const
 - move DT cell size check into the core to avoid code duplication
   in the drivers
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Merge tag 'reset-for-4.6' of git://git.pengutronix.de/git/pza/linux into next/drivers

Reset controller changes for v4.6

- add support for the imgtec Pistachio SoC reset controller
- make struct reset_control_ops const
- move DT cell size check into the core to avoid code duplication
  in the drivers

* tag 'reset-for-4.6' of git://git.pengutronix.de/git/pza/linux:
  reset: sti: Make reset_control_ops const
  reset: zynq: Make reset_control_ops const
  reset: socfpga: Make reset_control_ops const
  reset: hi6220: Make reset_control_ops const
  reset: ath79: Make reset_control_ops const
  reset: lpc18xx: Make reset_control_ops const
  reset: sunxi: Make reset_control_ops const
  reset: img: Make reset_control_ops const
  reset: berlin: Make reset_control_ops const
  reset: berlin: drop DT cell size check
  reset: img: Add Pistachio reset controller driver
  reset: img: Add pistachio reset controller binding document
  reset: hisilicon: check return value of reset_controller_register()
  reset: Move DT cell size check to the core
  reset: Make reset_control_ops const
  reset: remove unnecessary local variable initialization from of_reset_control_get_by_index

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-02-24 17:20:40 -08:00
commit 3f2242ec40
14 changed files with 262 additions and 19 deletions

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@ -0,0 +1,55 @@
Pistachio Reset Controller
=============================================================================
This binding describes a reset controller device that is used to enable and
disable individual IP blocks within the Pistachio SoC using "soft reset"
control bits found in the Pistachio SoC top level registers.
The actual action taken when soft reset is asserted is hardware dependent.
However, when asserted it may not be possible to access the hardware's
registers, and following an assert/deassert sequence the hardware's previous
state may no longer be valid.
Please refer to Documentation/devicetree/bindings/reset/reset.txt
for common reset controller binding usage.
Required properties:
- compatible: Contains "img,pistachio-reset"
- #reset-cells: Contains 1
Example:
cr_periph: clk@18148000 {
compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd";
reg = <0x18148000 0x1000>;
clocks = <&clk_periph PERIPH_CLK_SYS>;
clock-names = "sys";
#clock-cells = <1>;
pistachio_reset: reset-controller {
compatible = "img,pistachio-reset";
#reset-cells = <1>;
};
};
Specifying reset control of devices
=======================================
Device nodes should specify the reset channel required in their "resets"
property, containing a phandle to the pistachio reset device node and an
index specifying which reset to use, as described in
Documentation/devicetree/bindings/reset/reset.txt.
Example:
spdif_out: spdif-out@18100d00 {
...
resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
reset-names = "rst";
...
};
Macro definitions for the supported resets can be found in:
include/dt-bindings/reset/pistachio-resets.h

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@ -2,6 +2,7 @@ obj-y += core.o
obj-$(CONFIG_ARCH_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_ARCH_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_MACH_PISTACHIO) += reset-pistachio.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/ obj-$(CONFIG_ARCH_STI) += sti/
obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-$(CONFIG_ARCH_HISI) += hisilicon/

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@ -45,9 +45,6 @@ struct reset_control {
static int of_reset_simple_xlate(struct reset_controller_dev *rcdev, static int of_reset_simple_xlate(struct reset_controller_dev *rcdev,
const struct of_phandle_args *reset_spec) const struct of_phandle_args *reset_spec)
{ {
if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
return -EINVAL;
if (reset_spec->args[0] >= rcdev->nr_resets) if (reset_spec->args[0] >= rcdev->nr_resets)
return -EINVAL; return -EINVAL;
@ -152,7 +149,7 @@ EXPORT_SYMBOL_GPL(reset_control_status);
struct reset_control *of_reset_control_get_by_index(struct device_node *node, struct reset_control *of_reset_control_get_by_index(struct device_node *node,
int index) int index)
{ {
struct reset_control *rstc = ERR_PTR(-EPROBE_DEFER); struct reset_control *rstc;
struct reset_controller_dev *r, *rcdev; struct reset_controller_dev *r, *rcdev;
struct of_phandle_args args; struct of_phandle_args args;
int rstc_id; int rstc_id;
@ -178,6 +175,11 @@ struct reset_control *of_reset_control_get_by_index(struct device_node *node,
return ERR_PTR(-EPROBE_DEFER); return ERR_PTR(-EPROBE_DEFER);
} }
if (WARN_ON(args.args_count != rcdev->of_reset_n_cells)) {
mutex_unlock(&reset_controller_list_mutex);
return ERR_PTR(-EINVAL);
}
rstc_id = rcdev->of_xlate(rcdev, &args); rstc_id = rcdev->of_xlate(rcdev, &args);
if (rstc_id < 0) { if (rstc_id < 0) {
mutex_unlock(&reset_controller_list_mutex); mutex_unlock(&reset_controller_list_mutex);

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@ -57,7 +57,7 @@ static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
return 0; return 0;
} }
static struct reset_control_ops hi6220_reset_ops = { static const struct reset_control_ops hi6220_reset_ops = {
.assert = hi6220_reset_assert, .assert = hi6220_reset_assert,
.deassert = hi6220_reset_deassert, .deassert = hi6220_reset_deassert,
}; };
@ -83,9 +83,7 @@ static int hi6220_reset_probe(struct platform_device *pdev)
data->rc_dev.ops = &hi6220_reset_ops; data->rc_dev.ops = &hi6220_reset_ops;
data->rc_dev.of_node = pdev->dev.of_node; data->rc_dev.of_node = pdev->dev.of_node;
reset_controller_register(&data->rc_dev); return reset_controller_register(&data->rc_dev);
return 0;
} }
static const struct of_device_id hi6220_reset_match[] = { static const struct of_device_id hi6220_reset_match[] = {

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@ -70,7 +70,7 @@ static int ath79_reset_status(struct reset_controller_dev *rcdev,
return !!(val & BIT(id)); return !!(val & BIT(id));
} }
static struct reset_control_ops ath79_reset_ops = { static const struct reset_control_ops ath79_reset_ops = {
.assert = ath79_reset_assert, .assert = ath79_reset_assert,
.deassert = ath79_reset_deassert, .deassert = ath79_reset_deassert,
.status = ath79_reset_status, .status = ath79_reset_status,

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@ -46,7 +46,7 @@ static int berlin_reset_reset(struct reset_controller_dev *rcdev,
return 0; return 0;
} }
static struct reset_control_ops berlin_reset_ops = { static const struct reset_control_ops berlin_reset_ops = {
.reset = berlin_reset_reset, .reset = berlin_reset_reset,
}; };
@ -55,9 +55,6 @@ static int berlin_reset_xlate(struct reset_controller_dev *rcdev,
{ {
unsigned offset, bit; unsigned offset, bit;
if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
return -EINVAL;
offset = reset_spec->args[0]; offset = reset_spec->args[0];
bit = reset_spec->args[1]; bit = reset_spec->args[1];

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@ -136,7 +136,7 @@ static int lpc18xx_rgu_status(struct reset_controller_dev *rcdev,
return !(readl(rc->base + offset) & bit); return !(readl(rc->base + offset) & bit);
} }
static struct reset_control_ops lpc18xx_rgu_ops = { static const struct reset_control_ops lpc18xx_rgu_ops = {
.reset = lpc18xx_rgu_reset, .reset = lpc18xx_rgu_reset,
.assert = lpc18xx_rgu_assert, .assert = lpc18xx_rgu_assert,
.deassert = lpc18xx_rgu_deassert, .deassert = lpc18xx_rgu_deassert,

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@ -0,0 +1,154 @@
/*
* Pistachio SoC Reset Controller driver
*
* Copyright (C) 2015 Imagination Technologies Ltd.
*
* Author: Damien Horsley <Damien.Horsley@imgtec.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <dt-bindings/reset/pistachio-resets.h>
#define PISTACHIO_SOFT_RESET 0
struct pistachio_reset_data {
struct reset_controller_dev rcdev;
struct regmap *periph_regs;
};
static inline int pistachio_reset_shift(unsigned long id)
{
switch (id) {
case PISTACHIO_RESET_I2C0:
case PISTACHIO_RESET_I2C1:
case PISTACHIO_RESET_I2C2:
case PISTACHIO_RESET_I2C3:
case PISTACHIO_RESET_I2S_IN:
case PISTACHIO_RESET_PRL_OUT:
case PISTACHIO_RESET_SPDIF_OUT:
case PISTACHIO_RESET_SPI:
case PISTACHIO_RESET_PWM_PDM:
case PISTACHIO_RESET_UART0:
case PISTACHIO_RESET_UART1:
case PISTACHIO_RESET_QSPI:
case PISTACHIO_RESET_MDC:
case PISTACHIO_RESET_SDHOST:
case PISTACHIO_RESET_ETHERNET:
case PISTACHIO_RESET_IR:
case PISTACHIO_RESET_HASH:
case PISTACHIO_RESET_TIMER:
return id;
case PISTACHIO_RESET_I2S_OUT:
case PISTACHIO_RESET_SPDIF_IN:
case PISTACHIO_RESET_EVT:
return id + 6;
case PISTACHIO_RESET_USB_H:
case PISTACHIO_RESET_USB_PR:
case PISTACHIO_RESET_USB_PHY_PR:
case PISTACHIO_RESET_USB_PHY_PON:
return id + 7;
default:
return -EINVAL;
}
}
static int pistachio_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct pistachio_reset_data *rd;
u32 mask;
int shift;
rd = container_of(rcdev, struct pistachio_reset_data, rcdev);
shift = pistachio_reset_shift(id);
if (shift < 0)
return shift;
mask = BIT(shift);
return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET,
mask, mask);
}
static int pistachio_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct pistachio_reset_data *rd;
u32 mask;
int shift;
rd = container_of(rcdev, struct pistachio_reset_data, rcdev);
shift = pistachio_reset_shift(id);
if (shift < 0)
return shift;
mask = BIT(shift);
return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET,
mask, 0);
}
static const struct reset_control_ops pistachio_reset_ops = {
.assert = pistachio_reset_assert,
.deassert = pistachio_reset_deassert,
};
static int pistachio_reset_probe(struct platform_device *pdev)
{
struct pistachio_reset_data *rd;
struct device *dev = &pdev->dev;
struct device_node *np = pdev->dev.of_node;
rd = devm_kzalloc(dev, sizeof(*rd), GFP_KERNEL);
if (!rd)
return -ENOMEM;
rd->periph_regs = syscon_node_to_regmap(np->parent);
if (IS_ERR(rd->periph_regs))
return PTR_ERR(rd->periph_regs);
rd->rcdev.owner = THIS_MODULE;
rd->rcdev.nr_resets = PISTACHIO_RESET_MAX + 1;
rd->rcdev.ops = &pistachio_reset_ops;
rd->rcdev.of_node = np;
return reset_controller_register(&rd->rcdev);
}
static int pistachio_reset_remove(struct platform_device *pdev)
{
struct pistachio_reset_data *data = platform_get_drvdata(pdev);
reset_controller_unregister(&data->rcdev);
return 0;
}
static const struct of_device_id pistachio_reset_dt_ids[] = {
{ .compatible = "img,pistachio-reset", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, pistachio_reset_dt_ids);
static struct platform_driver pistachio_reset_driver = {
.probe = pistachio_reset_probe,
.remove = pistachio_reset_remove,
.driver = {
.name = "pistachio-reset",
.of_match_table = pistachio_reset_dt_ids,
},
};
module_platform_driver(pistachio_reset_driver);
MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
MODULE_DESCRIPTION("Pistacho Reset Controller Driver");
MODULE_LICENSE("GPL v2");

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@ -90,7 +90,7 @@ static int socfpga_reset_status(struct reset_controller_dev *rcdev,
return !(reg & BIT(offset)); return !(reg & BIT(offset));
} }
static struct reset_control_ops socfpga_reset_ops = { static const struct reset_control_ops socfpga_reset_ops = {
.assert = socfpga_reset_assert, .assert = socfpga_reset_assert,
.deassert = socfpga_reset_deassert, .deassert = socfpga_reset_deassert,
.status = socfpga_reset_status, .status = socfpga_reset_status,

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@ -70,7 +70,7 @@ static int sunxi_reset_deassert(struct reset_controller_dev *rcdev,
return 0; return 0;
} }
static struct reset_control_ops sunxi_reset_ops = { static const struct reset_control_ops sunxi_reset_ops = {
.assert = sunxi_reset_assert, .assert = sunxi_reset_assert,
.deassert = sunxi_reset_deassert, .deassert = sunxi_reset_deassert,
}; };

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@ -86,7 +86,7 @@ static int zynq_reset_status(struct reset_controller_dev *rcdev,
return !!(reg & BIT(offset)); return !!(reg & BIT(offset));
} }
static struct reset_control_ops zynq_reset_ops = { static const struct reset_control_ops zynq_reset_ops = {
.assert = zynq_reset_assert, .assert = zynq_reset_assert,
.deassert = zynq_reset_deassert, .deassert = zynq_reset_deassert,
.status = zynq_reset_status, .status = zynq_reset_status,

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@ -134,7 +134,7 @@ static int syscfg_reset_status(struct reset_controller_dev *rcdev,
return rst->active_low ? !ret_val : !!ret_val; return rst->active_low ? !ret_val : !!ret_val;
} }
static struct reset_control_ops syscfg_reset_ops = { static const struct reset_control_ops syscfg_reset_ops = {
.reset = syscfg_reset_dev, .reset = syscfg_reset_dev,
.assert = syscfg_reset_assert, .assert = syscfg_reset_assert,
.deassert = syscfg_reset_deassert, .deassert = syscfg_reset_deassert,

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@ -0,0 +1,36 @@
/*
* This header provides constants for the reset controller
* present in the Pistachio SoC
*/
#ifndef _PISTACHIO_RESETS_H
#define _PISTACHIO_RESETS_H
#define PISTACHIO_RESET_I2C0 0
#define PISTACHIO_RESET_I2C1 1
#define PISTACHIO_RESET_I2C2 2
#define PISTACHIO_RESET_I2C3 3
#define PISTACHIO_RESET_I2S_IN 4
#define PISTACHIO_RESET_PRL_OUT 5
#define PISTACHIO_RESET_SPDIF_OUT 6
#define PISTACHIO_RESET_SPI 7
#define PISTACHIO_RESET_PWM_PDM 8
#define PISTACHIO_RESET_UART0 9
#define PISTACHIO_RESET_UART1 10
#define PISTACHIO_RESET_QSPI 11
#define PISTACHIO_RESET_MDC 12
#define PISTACHIO_RESET_SDHOST 13
#define PISTACHIO_RESET_ETHERNET 14
#define PISTACHIO_RESET_IR 15
#define PISTACHIO_RESET_HASH 16
#define PISTACHIO_RESET_TIMER 17
#define PISTACHIO_RESET_I2S_OUT 18
#define PISTACHIO_RESET_SPDIF_IN 19
#define PISTACHIO_RESET_EVT 20
#define PISTACHIO_RESET_USB_H 21
#define PISTACHIO_RESET_USB_PR 22
#define PISTACHIO_RESET_USB_PHY_PR 23
#define PISTACHIO_RESET_USB_PHY_PON 24
#define PISTACHIO_RESET_MAX 24
#endif

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@ -38,7 +38,7 @@ struct of_phandle_args;
* @nr_resets: number of reset controls in this reset controller device * @nr_resets: number of reset controls in this reset controller device
*/ */
struct reset_controller_dev { struct reset_controller_dev {
struct reset_control_ops *ops; const struct reset_control_ops *ops;
struct module *owner; struct module *owner;
struct list_head list; struct list_head list;
struct device_node *of_node; struct device_node *of_node;