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[ALSA] ASoC pxa2xx I2S support
This patch adds pxa2xx I2S ASoC audio support. Features:- o Supports playback/capture o 16 bit PCM o 8k - 96k sample rates o Supports master and slave mode. From: Liam Girdwood <liam.girdwood@wolfsonmicro.com> Signed-off-by: Richard Purdie <rpurdie@rpsys.net> Signed-off-by: Liam Girdwood <liam.girdwood@wolfsonmicro.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
This commit is contained in:
Liam Girdwood
Jaroslav Kysela
parent
f11a96d5cd
commit
3e7cc3d3d1
306
sound/soc/pxa/pxa2xx-i2s.c
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306
sound/soc/pxa/pxa2xx-i2s.c
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@ -0,0 +1,306 @@
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/*
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* pxa2xx-i2s.c -- ALSA Soc Audio Layer
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*
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* Copyright 2005 Wolfson Microelectronics PLC.
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* Author: Liam Girdwood
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* liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Revision history
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* 12th Aug 2005 Initial version.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <sound/driver.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <asm/hardware.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/audio.h>
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#include "pxa2xx-pcm.h"
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/* used to disable sysclk if external crystal is used */
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static int extclk;
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module_param(extclk, int, 0);
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MODULE_PARM_DESC(extclk, "set to 1 to disable pxa2xx i2s sysclk");
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struct pxa_i2s_port {
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u32 sadiv;
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u32 sacr0;
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u32 sacr1;
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u32 saimr;
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int master;
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};
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static struct pxa_i2s_port pxa_i2s;
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#define PXA_I2S_DAIFMT \
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(SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF)
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#define PXA_I2S_DIR \
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(SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
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#define PXA_I2S_RATES \
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(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
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SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
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/* priv is divider */
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static struct snd_soc_dai_mode pxa2xx_i2s_modes[] = {
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/* pxa2xx I2S frame and clock master modes */
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{PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
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SNDRV_PCM_FMTBIT_S16_LE, SNDRV_PCM_RATE_8000, PXA_I2S_DIR,
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SND_SOC_DAI_BFS_DIV, 256, SND_SOC_FSBD(4), 0x48},
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{PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
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SNDRV_PCM_FMTBIT_S16_LE, SNDRV_PCM_RATE_11025, PXA_I2S_DIR,
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SND_SOC_DAI_BFS_DIV, 256, SND_SOC_FSBD(4), 0x34},
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{PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
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SNDRV_PCM_FMTBIT_S16_LE, SNDRV_PCM_RATE_16000, PXA_I2S_DIR,
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SND_SOC_DAI_BFS_DIV, 256, SND_SOC_FSBD(4), 0x24},
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{PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
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SNDRV_PCM_FMTBIT_S16_LE, SNDRV_PCM_RATE_22050, PXA_I2S_DIR,
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SND_SOC_DAI_BFS_DIV, 256, SND_SOC_FSBD(4), 0x1a},
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{PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
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SNDRV_PCM_FMTBIT_S16_LE, SNDRV_PCM_RATE_44100, PXA_I2S_DIR,
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SND_SOC_DAI_BFS_DIV, 256, SND_SOC_FSBD(4), 0xd},
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{PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
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SNDRV_PCM_FMTBIT_S16_LE, SNDRV_PCM_RATE_48000, PXA_I2S_DIR,
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SND_SOC_DAI_BFS_DIV, 256, SND_SOC_FSBD(4), 0xc},
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/* pxa2xx I2S frame master and clock slave mode */
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{PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBM_CFS, SND_SOC_DAITDM_LRDW(0,0),
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SNDRV_PCM_FMTBIT_S16_LE, PXA_I2S_RATES, PXA_I2S_DIR, 0,
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SND_SOC_FS_ALL, SND_SOC_FSB(64), 0x48},
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};
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static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
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.name = "I2S PCM Stereo out",
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.dev_addr = __PREG(SADR),
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.drcmr = &DRCMRTXSADR,
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST32 | DCMD_WIDTH4,
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};
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static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
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.name = "I2S PCM Stereo in",
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.dev_addr = __PREG(SADR),
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.drcmr = &DRCMRRXSADR,
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST32 | DCMD_WIDTH4,
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};
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static struct pxa2xx_gpio gpio_bus[] = {
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{ /* I2S SoC Slave */
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.rx = GPIO29_SDATA_IN_I2S_MD,
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.tx = GPIO30_SDATA_OUT_I2S_MD,
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.clk = GPIO28_BITCLK_IN_I2S_MD,
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.frm = GPIO31_SYNC_I2S_MD,
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},
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{ /* I2S SoC Master */
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#ifdef CONFIG_PXA27x
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.sys = GPIO113_I2S_SYSCLK_MD,
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#else
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.sys = GPIO32_SYSCLK_I2S_MD,
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#endif
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.rx = GPIO29_SDATA_IN_I2S_MD,
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.tx = GPIO30_SDATA_OUT_I2S_MD,
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.clk = GPIO28_BITCLK_OUT_I2S_MD,
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.frm = GPIO31_SYNC_I2S_MD,
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},
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};
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static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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if (!rtd->cpu_dai->active) {
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SACR0 |= SACR0_RST;
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SACR0 = 0;
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}
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return 0;
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}
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/* wait for I2S controller to be ready */
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static int pxa_i2s_wait(void)
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{
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int i;
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/* flush the Rx FIFO */
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for(i = 0; i < 16; i++)
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SADR;
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return 0;
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}
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static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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pxa_i2s.master = 0;
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if (rtd->cpu_dai->dai_runtime.fmt & SND_SOC_DAIFMT_CBS_CFS)
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pxa_i2s.master = 1;
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if (pxa_i2s.master && !extclk)
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pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);
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pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
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pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
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pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
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pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
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pxa_set_cken(CKEN8_I2S, 1);
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pxa_i2s_wait();
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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rtd->cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
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else
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rtd->cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
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/* is port used by another stream */
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if (!(SACR0 & SACR0_ENB)) {
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SACR0 = 0;
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SACR1 = 0;
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if (pxa_i2s.master)
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SACR0 |= SACR0_BCKD;
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SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
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if (rtd->cpu_dai->dai_runtime.fmt & SND_SOC_DAIFMT_LEFT_J)
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SACR1 |= SACR1_AMSL;
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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SAIMR |= SAIMR_TFS;
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else
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SAIMR |= SAIMR_RFS;
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SADIV = rtd->cpu_dai->dai_runtime.priv;
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return 0;
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}
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static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
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{
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int ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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SACR0 |= SACR0_ENB;
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break;
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
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{
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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SACR1 |= SACR1_DRPL;
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SAIMR &= ~SAIMR_TFS;
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} else {
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SACR1 |= SACR1_DREC;
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SAIMR &= ~SAIMR_RFS;
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}
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if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
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SACR0 &= ~SACR0_ENB;
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pxa_i2s_wait();
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pxa_set_cken(CKEN8_I2S, 0);
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}
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}
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#ifdef CONFIG_PM
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static int pxa2xx_i2s_suspend(struct platform_device *dev,
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struct snd_soc_cpu_dai *dai)
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{
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if (!dai->active)
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return 0;
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/* store registers */
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pxa_i2s.sacr0 = SACR0;
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pxa_i2s.sacr1 = SACR1;
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pxa_i2s.saimr = SAIMR;
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pxa_i2s.sadiv = SADIV;
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/* deactivate link */
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SACR0 &= ~SACR0_ENB;
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pxa_i2s_wait();
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return 0;
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}
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static int pxa2xx_i2s_resume(struct platform_device *pdev,
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struct snd_soc_cpu_dai *dai)
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{
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if (!dai->active)
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return 0;
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pxa_i2s_wait();
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SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
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SACR1 = pxa_i2s.sacr1;
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SAIMR = pxa_i2s.saimr;
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SADIV = pxa_i2s.sadiv;
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SACR0 |= SACR0_ENB;
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return 0;
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}
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#else
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#define pxa2xx_i2s_suspend NULL
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#define pxa2xx_i2s_resume NULL
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#endif
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/* pxa2xx I2S sysclock is always 256 FS */
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static unsigned int pxa_i2s_config_sysclk(struct snd_soc_cpu_dai *iface,
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struct snd_soc_clock_info *info, unsigned int clk)
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{
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return info->rate << 8;
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}
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struct snd_soc_cpu_dai pxa_i2s_dai = {
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.name = "pxa2xx-i2s",
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.id = 0,
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.type = SND_SOC_DAI_I2S,
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.suspend = pxa2xx_i2s_suspend,
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.resume = pxa2xx_i2s_resume,
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.config_sysclk = pxa_i2s_config_sysclk,
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.playback = {
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.channels_min = 2,
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.channels_max = 2,},
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.capture = {
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.channels_min = 2,
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.channels_max = 2,},
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.ops = {
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.startup = pxa2xx_i2s_startup,
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.shutdown = pxa2xx_i2s_shutdown,
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.trigger = pxa2xx_i2s_trigger,
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.hw_params = pxa2xx_i2s_hw_params,},
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.caps = {
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.num_modes = ARRAY_SIZE(pxa2xx_i2s_modes),
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.mode = pxa2xx_i2s_modes,},
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};
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EXPORT_SYMBOL_GPL(pxa_i2s_dai);
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/* Module information */
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MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com");
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MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
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MODULE_LICENSE("GPL");
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