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drm/i915: Move i915_power_well_id out of i915_reg.h

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It has nothing to do with registers, so move it to the more appropriate
intel_display_power.h

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190816012343.36433-2-daniele.ceraolospurio@intel.com
This commit is contained in:
Daniele Ceraolo Spurio 2019-08-15 18:23:38 -07:00 committed by Chris Wilson
parent df40306902
commit 3e5d0641e8
4 changed files with 23 additions and 21 deletions
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1
drivers/gpu/drm/i915/display/intel_display_power.c
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@ -13,6 +13,7 @@
#include "intel_cdclk.h" #include "intel_cdclk.h"
#include "intel_combo_phy.h" #include "intel_combo_phy.h"
#include "intel_csr.h" #include "intel_csr.h"
#include "intel_display_power.h"
#include "intel_display_types.h" #include "intel_display_types.h"
#include "intel_dpio_phy.h" #include "intel_dpio_phy.h"
#include "intel_hotplug.h" #include "intel_hotplug.h"

21
drivers/gpu/drm/i915/display/intel_display_power.h
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@ -92,6 +92,27 @@ enum intel_display_power_domain {
POWER_DOMAIN_NUM, POWER_DOMAIN_NUM,
}; };
/*
* i915_power_well_id:
*
* IDs used to look up power wells. Power wells accessed directly bypassing
* the power domains framework must be assigned a unique ID. The rest of power
* wells must be assigned DISP_PW_ID_NONE.
*/
enum i915_power_well_id {
DISP_PW_ID_NONE,
VLV_DISP_PW_DISP2D,
BXT_DISP_PW_DPIO_CMN_A,
VLV_DISP_PW_DPIO_CMN_BC,
GLK_DISP_PW_DPIO_CMN_C,
CHV_DISP_PW_DPIO_CMN_D,
HSW_DISP_PW_GLOBAL,
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
};
#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)

1
drivers/gpu/drm/i915/display/intel_hdcp.c
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@ -14,6 +14,7 @@
#include <drm/i915_component.h> #include <drm/i915_component.h>
#include "i915_reg.h" #include "i915_reg.h"
#include "intel_display_power.h"
#include "intel_display_types.h" #include "intel_display_types.h"
#include "intel_hdcp.h" #include "intel_hdcp.h"
#include "intel_sideband.h" #include "intel_sideband.h"

21
drivers/gpu/drm/i915/i915_reg.h
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@ -1163,27 +1163,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define PUNIT_REG_ISPSSPM0 0x39 #define PUNIT_REG_ISPSSPM0 0x39
#define PUNIT_REG_ISPSSPM1 0x3a #define PUNIT_REG_ISPSSPM1 0x3a
/*
* i915_power_well_id:
*
* IDs used to look up power wells. Power wells accessed directly bypassing
* the power domains framework must be assigned a unique ID. The rest of power
* wells must be assigned DISP_PW_ID_NONE.
*/
enum i915_power_well_id {
DISP_PW_ID_NONE,
VLV_DISP_PW_DISP2D,
BXT_DISP_PW_DPIO_CMN_A,
VLV_DISP_PW_DPIO_CMN_BC,
GLK_DISP_PW_DPIO_CMN_C,
CHV_DISP_PW_DPIO_CMN_D,
HSW_DISP_PW_GLOBAL,
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
};
#define PUNIT_REG_PWRGT_CTRL 0x60 #define PUNIT_REG_PWRGT_CTRL 0x60
#define PUNIT_REG_PWRGT_STATUS 0x61 #define PUNIT_REG_PWRGT_STATUS 0x61
#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))