mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
Merge branch 'mlx5_packet_pacing' into rdma.git for-next
Yishai Hadas Says: ==================== Expose raw packet pacing APIs to be used by DEVX based applications. The existing code was refactored to have a single flow with the new raw APIs. ==================== Based on the mlx5-next branch at git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux Due to dependencies * branch 'mlx5_packet_pacing': IB/mlx5: Introduce UAPIs to manage packet pacing net/mlx5: Expose raw packet pacing APIs
This commit is contained in:
commit
3e3cf2e82c
drivers
infiniband/hw/mlx5
net/ethernet/mellanox/mlx5/core
include
@ -8,3 +8,4 @@ mlx5_ib-$(CONFIG_INFINIBAND_ON_DEMAND_PAGING) += odp.o
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mlx5_ib-$(CONFIG_MLX5_ESWITCH) += ib_rep.o
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mlx5_ib-$(CONFIG_INFINIBAND_USER_ACCESS) += devx.o
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mlx5_ib-$(CONFIG_INFINIBAND_USER_ACCESS) += flow.o
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mlx5_ib-$(CONFIG_INFINIBAND_USER_ACCESS) += qos.o
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|
@ -6251,6 +6251,7 @@ ADD_UVERBS_ATTRIBUTES_SIMPLE(
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static const struct uapi_definition mlx5_ib_defs[] = {
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UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
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UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
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UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
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UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
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&mlx5_ib_flow_action),
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|
@ -203,6 +203,11 @@ struct mlx5_ib_flow_matcher {
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u8 match_criteria_enable;
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};
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struct mlx5_ib_pp {
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u16 index;
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struct mlx5_core_dev *mdev;
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};
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struct mlx5_ib_flow_db {
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struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
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struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT];
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@ -1383,6 +1388,7 @@ int mlx5_ib_fill_stat_entry(struct sk_buff *msg,
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extern const struct uapi_definition mlx5_ib_devx_defs[];
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extern const struct uapi_definition mlx5_ib_flow_defs[];
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extern const struct uapi_definition mlx5_ib_qos_defs[];
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#if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
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int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user);
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136
drivers/infiniband/hw/mlx5/qos.c
Normal file
136
drivers/infiniband/hw/mlx5/qos.c
Normal file
@ -0,0 +1,136 @@
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// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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/*
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* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved.
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*/
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#include <rdma/uverbs_ioctl.h>
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#include <rdma/mlx5_user_ioctl_cmds.h>
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#include <rdma/mlx5_user_ioctl_verbs.h>
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#include <linux/mlx5/driver.h>
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#include "mlx5_ib.h"
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#define UVERBS_MODULE_NAME mlx5_ib
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#include <rdma/uverbs_named_ioctl.h>
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static bool pp_is_supported(struct ib_device *device)
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{
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struct mlx5_ib_dev *dev = to_mdev(device);
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return (MLX5_CAP_GEN(dev->mdev, qos) &&
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MLX5_CAP_QOS(dev->mdev, packet_pacing) &&
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MLX5_CAP_QOS(dev->mdev, packet_pacing_uid));
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}
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static int UVERBS_HANDLER(MLX5_IB_METHOD_PP_OBJ_ALLOC)(
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struct uverbs_attr_bundle *attrs)
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{
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u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {};
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struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs,
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MLX5_IB_ATTR_PP_OBJ_ALLOC_HANDLE);
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struct mlx5_ib_dev *dev;
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struct mlx5_ib_ucontext *c;
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struct mlx5_ib_pp *pp_entry;
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void *in_ctx;
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u16 uid;
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int inlen;
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u32 flags;
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int err;
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c = to_mucontext(ib_uverbs_get_ucontext(attrs));
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if (IS_ERR(c))
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return PTR_ERR(c);
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/* The allocated entry can be used only by a DEVX context */
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if (!c->devx_uid)
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return -EINVAL;
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dev = to_mdev(c->ibucontext.device);
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pp_entry = kzalloc(sizeof(*pp_entry), GFP_KERNEL);
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if (IS_ERR(pp_entry))
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return PTR_ERR(pp_entry);
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in_ctx = uverbs_attr_get_alloced_ptr(attrs,
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MLX5_IB_ATTR_PP_OBJ_ALLOC_CTX);
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inlen = uverbs_attr_get_len(attrs,
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MLX5_IB_ATTR_PP_OBJ_ALLOC_CTX);
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memcpy(rl_raw, in_ctx, inlen);
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err = uverbs_get_flags32(&flags, attrs,
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MLX5_IB_ATTR_PP_OBJ_ALLOC_FLAGS,
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MLX5_IB_UAPI_PP_ALLOC_FLAGS_DEDICATED_INDEX);
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if (err)
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goto err;
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uid = (flags & MLX5_IB_UAPI_PP_ALLOC_FLAGS_DEDICATED_INDEX) ?
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c->devx_uid : MLX5_SHARED_RESOURCE_UID;
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err = mlx5_rl_add_rate_raw(dev->mdev, rl_raw, uid,
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(flags & MLX5_IB_UAPI_PP_ALLOC_FLAGS_DEDICATED_INDEX),
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&pp_entry->index);
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if (err)
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goto err;
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err = uverbs_copy_to(attrs, MLX5_IB_ATTR_PP_OBJ_ALLOC_INDEX,
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&pp_entry->index, sizeof(pp_entry->index));
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if (err)
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goto clean;
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pp_entry->mdev = dev->mdev;
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uobj->object = pp_entry;
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return 0;
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clean:
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mlx5_rl_remove_rate_raw(dev->mdev, pp_entry->index);
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err:
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kfree(pp_entry);
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return err;
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}
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static int pp_obj_cleanup(struct ib_uobject *uobject,
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enum rdma_remove_reason why,
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struct uverbs_attr_bundle *attrs)
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{
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struct mlx5_ib_pp *pp_entry = uobject->object;
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mlx5_rl_remove_rate_raw(pp_entry->mdev, pp_entry->index);
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kfree(pp_entry);
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return 0;
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}
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DECLARE_UVERBS_NAMED_METHOD(
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MLX5_IB_METHOD_PP_OBJ_ALLOC,
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UVERBS_ATTR_IDR(MLX5_IB_ATTR_PP_OBJ_ALLOC_HANDLE,
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MLX5_IB_OBJECT_PP,
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UVERBS_ACCESS_NEW,
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UA_MANDATORY),
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UVERBS_ATTR_PTR_IN(
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MLX5_IB_ATTR_PP_OBJ_ALLOC_CTX,
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UVERBS_ATTR_SIZE(1,
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MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)),
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UA_MANDATORY,
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UA_ALLOC_AND_COPY),
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UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_PP_OBJ_ALLOC_FLAGS,
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enum mlx5_ib_uapi_pp_alloc_flags,
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UA_MANDATORY),
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UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_PP_OBJ_ALLOC_INDEX,
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UVERBS_ATTR_TYPE(u16),
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UA_MANDATORY));
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DECLARE_UVERBS_NAMED_METHOD_DESTROY(
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MLX5_IB_METHOD_PP_OBJ_DESTROY,
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UVERBS_ATTR_IDR(MLX5_IB_ATTR_PP_OBJ_DESTROY_HANDLE,
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MLX5_IB_OBJECT_PP,
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UVERBS_ACCESS_DESTROY,
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UA_MANDATORY));
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DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_PP,
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UVERBS_TYPE_ALLOC_IDR(pp_obj_cleanup),
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&UVERBS_METHOD(MLX5_IB_METHOD_PP_OBJ_ALLOC),
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&UVERBS_METHOD(MLX5_IB_METHOD_PP_OBJ_DESTROY));
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const struct uapi_definition mlx5_ib_qos_defs[] = {
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UAPI_DEF_CHAIN_OBJ_TREE_NAMED(
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MLX5_IB_OBJECT_PP,
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UAPI_DEF_IS_OBJ_SUPPORTED(pp_is_supported)),
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{},
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};
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@ -204,7 +204,7 @@ struct mlx5e_tx_wqe {
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struct mlx5e_rx_wqe_ll {
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struct mlx5_wqe_srq_next_seg next;
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struct mlx5_wqe_data_seg data[0];
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struct mlx5_wqe_data_seg data[];
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};
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struct mlx5e_rx_wqe_cyc {
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@ -57,7 +57,7 @@ struct mlx5_fpga_ipsec_cmd_context {
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struct completion complete;
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struct mlx5_fpga_device *dev;
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struct list_head list; /* Item in pending_cmds */
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u8 command[0];
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u8 command[];
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};
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struct mlx5_fpga_esp_xfrm;
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|
@ -470,7 +470,7 @@ struct mlx5_fc_bulk {
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u32 base_id;
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int bulk_len;
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unsigned long *bitmask;
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struct mlx5_fc fcs[0];
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struct mlx5_fc fcs[];
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};
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static void mlx5_fc_init(struct mlx5_fc *counter, struct mlx5_fc_bulk *bulk,
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|
@ -56,7 +56,7 @@ struct mlx5i_priv {
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u32 qkey;
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u16 pkey_index;
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struct mlx5i_pkey_qpn_ht *qpn_htbl;
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char *mlx5e_priv[0];
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char *mlx5e_priv[];
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};
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int mlx5i_create_tis(struct mlx5_core_dev *mdev, u32 underlay_qpn, u32 *tisn);
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@ -107,7 +107,7 @@ struct mlx5i_tx_wqe {
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struct mlx5_wqe_datagram_seg datagram;
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struct mlx5_wqe_eth_pad pad;
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struct mlx5_wqe_eth_seg eth;
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struct mlx5_wqe_data_seg data[0];
|
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struct mlx5_wqe_data_seg data[];
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};
|
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|
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static inline void mlx5i_sq_fetch_wqe(struct mlx5e_txqsq *sq,
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|
@ -101,22 +101,39 @@ int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
|
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return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
|
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}
|
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|
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static bool mlx5_rl_are_equal_raw(struct mlx5_rl_entry *entry, void *rl_in,
|
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u16 uid)
|
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{
|
||||
return (!memcmp(entry->rl_raw, rl_in, sizeof(entry->rl_raw)) &&
|
||||
entry->uid == uid);
|
||||
}
|
||||
|
||||
/* Finds an entry where we can register the given rate
|
||||
* If the rate already exists, return the entry where it is registered,
|
||||
* otherwise return the first available entry.
|
||||
* If the table is full, return NULL
|
||||
*/
|
||||
static struct mlx5_rl_entry *find_rl_entry(struct mlx5_rl_table *table,
|
||||
struct mlx5_rate_limit *rl)
|
||||
void *rl_in, u16 uid, bool dedicated)
|
||||
{
|
||||
struct mlx5_rl_entry *ret_entry = NULL;
|
||||
bool empty_found = false;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < table->max_size; i++) {
|
||||
if (mlx5_rl_are_equal(&table->rl_entry[i].rl, rl))
|
||||
return &table->rl_entry[i];
|
||||
if (!empty_found && !table->rl_entry[i].rl.rate) {
|
||||
if (dedicated) {
|
||||
if (!table->rl_entry[i].refcount)
|
||||
return &table->rl_entry[i];
|
||||
continue;
|
||||
}
|
||||
|
||||
if (table->rl_entry[i].refcount) {
|
||||
if (table->rl_entry[i].dedicated)
|
||||
continue;
|
||||
if (mlx5_rl_are_equal_raw(&table->rl_entry[i], rl_in,
|
||||
uid))
|
||||
return &table->rl_entry[i];
|
||||
} else if (!empty_found) {
|
||||
empty_found = true;
|
||||
ret_entry = &table->rl_entry[i];
|
||||
}
|
||||
@ -126,18 +143,19 @@ static struct mlx5_rl_entry *find_rl_entry(struct mlx5_rl_table *table,
|
||||
}
|
||||
|
||||
static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev *dev,
|
||||
u16 index,
|
||||
struct mlx5_rate_limit *rl)
|
||||
struct mlx5_rl_entry *entry, bool set)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {0};
|
||||
u32 out[MLX5_ST_SZ_DW(set_pp_rate_limit_out)] = {0};
|
||||
u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {};
|
||||
u32 out[MLX5_ST_SZ_DW(set_pp_rate_limit_out)] = {};
|
||||
void *pp_context;
|
||||
|
||||
pp_context = MLX5_ADDR_OF(set_pp_rate_limit_in, in, ctx);
|
||||
MLX5_SET(set_pp_rate_limit_in, in, opcode,
|
||||
MLX5_CMD_OP_SET_PP_RATE_LIMIT);
|
||||
MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, index);
|
||||
MLX5_SET(set_pp_rate_limit_in, in, rate_limit, rl->rate);
|
||||
MLX5_SET(set_pp_rate_limit_in, in, burst_upper_bound, rl->max_burst_sz);
|
||||
MLX5_SET(set_pp_rate_limit_in, in, typical_packet_size, rl->typical_pkt_sz);
|
||||
MLX5_SET(set_pp_rate_limit_in, in, uid, entry->uid);
|
||||
MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, entry->index);
|
||||
if (set)
|
||||
memcpy(pp_context, entry->rl_raw, sizeof(entry->rl_raw));
|
||||
return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
|
||||
}
|
||||
|
||||
@ -158,23 +176,25 @@ bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_rl_are_equal);
|
||||
|
||||
int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
|
||||
struct mlx5_rate_limit *rl)
|
||||
int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
|
||||
bool dedicated_entry, u16 *index)
|
||||
{
|
||||
struct mlx5_rl_table *table = &dev->priv.rl_table;
|
||||
struct mlx5_rl_entry *entry;
|
||||
int err = 0;
|
||||
u32 rate;
|
||||
|
||||
rate = MLX5_GET(set_pp_rate_limit_context, rl_in, rate_limit);
|
||||
mutex_lock(&table->rl_lock);
|
||||
|
||||
if (!rl->rate || !mlx5_rl_is_in_range(dev, rl->rate)) {
|
||||
if (!rate || !mlx5_rl_is_in_range(dev, rate)) {
|
||||
mlx5_core_err(dev, "Invalid rate: %u, should be %u to %u\n",
|
||||
rl->rate, table->min_rate, table->max_rate);
|
||||
rate, table->min_rate, table->max_rate);
|
||||
err = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
entry = find_rl_entry(table, rl);
|
||||
entry = find_rl_entry(table, rl_in, uid, dedicated_entry);
|
||||
if (!entry) {
|
||||
mlx5_core_err(dev, "Max number of %u rates reached\n",
|
||||
table->max_size);
|
||||
@ -185,16 +205,24 @@ int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
|
||||
/* rate already configured */
|
||||
entry->refcount++;
|
||||
} else {
|
||||
memcpy(entry->rl_raw, rl_in, sizeof(entry->rl_raw));
|
||||
entry->uid = uid;
|
||||
/* new rate limit */
|
||||
err = mlx5_set_pp_rate_limit_cmd(dev, entry->index, rl);
|
||||
err = mlx5_set_pp_rate_limit_cmd(dev, entry, true);
|
||||
if (err) {
|
||||
mlx5_core_err(dev, "Failed configuring rate limit(err %d): rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
|
||||
err, rl->rate, rl->max_burst_sz,
|
||||
rl->typical_pkt_sz);
|
||||
mlx5_core_err(
|
||||
dev,
|
||||
"Failed configuring rate limit(err %d): rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
|
||||
err, rate,
|
||||
MLX5_GET(set_pp_rate_limit_context, rl_in,
|
||||
burst_upper_bound),
|
||||
MLX5_GET(set_pp_rate_limit_context, rl_in,
|
||||
typical_packet_size));
|
||||
goto out;
|
||||
}
|
||||
entry->rl = *rl;
|
||||
|
||||
entry->refcount = 1;
|
||||
entry->dedicated = dedicated_entry;
|
||||
}
|
||||
*index = entry->index;
|
||||
|
||||
@ -202,20 +230,61 @@ int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
|
||||
mutex_unlock(&table->rl_lock);
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_rl_add_rate_raw);
|
||||
|
||||
void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index)
|
||||
{
|
||||
struct mlx5_rl_table *table = &dev->priv.rl_table;
|
||||
struct mlx5_rl_entry *entry;
|
||||
|
||||
mutex_lock(&table->rl_lock);
|
||||
entry = &table->rl_entry[index - 1];
|
||||
entry->refcount--;
|
||||
if (!entry->refcount)
|
||||
/* need to remove rate */
|
||||
mlx5_set_pp_rate_limit_cmd(dev, entry, false);
|
||||
mutex_unlock(&table->rl_lock);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_rl_remove_rate_raw);
|
||||
|
||||
int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
|
||||
struct mlx5_rate_limit *rl)
|
||||
{
|
||||
u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {};
|
||||
|
||||
MLX5_SET(set_pp_rate_limit_context, rl_raw, rate_limit, rl->rate);
|
||||
MLX5_SET(set_pp_rate_limit_context, rl_raw, burst_upper_bound,
|
||||
rl->max_burst_sz);
|
||||
MLX5_SET(set_pp_rate_limit_context, rl_raw, typical_packet_size,
|
||||
rl->typical_pkt_sz);
|
||||
|
||||
return mlx5_rl_add_rate_raw(dev, rl_raw,
|
||||
MLX5_CAP_QOS(dev, packet_pacing_uid) ?
|
||||
MLX5_SHARED_RESOURCE_UID : 0,
|
||||
false, index);
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_rl_add_rate);
|
||||
|
||||
void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl)
|
||||
{
|
||||
u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {};
|
||||
struct mlx5_rl_table *table = &dev->priv.rl_table;
|
||||
struct mlx5_rl_entry *entry = NULL;
|
||||
struct mlx5_rate_limit reset_rl = {0};
|
||||
|
||||
/* 0 is a reserved value for unlimited rate */
|
||||
if (rl->rate == 0)
|
||||
return;
|
||||
|
||||
MLX5_SET(set_pp_rate_limit_context, rl_raw, rate_limit, rl->rate);
|
||||
MLX5_SET(set_pp_rate_limit_context, rl_raw, burst_upper_bound,
|
||||
rl->max_burst_sz);
|
||||
MLX5_SET(set_pp_rate_limit_context, rl_raw, typical_packet_size,
|
||||
rl->typical_pkt_sz);
|
||||
|
||||
mutex_lock(&table->rl_lock);
|
||||
entry = find_rl_entry(table, rl);
|
||||
entry = find_rl_entry(table, rl_raw,
|
||||
MLX5_CAP_QOS(dev, packet_pacing_uid) ?
|
||||
MLX5_SHARED_RESOURCE_UID : 0, false);
|
||||
if (!entry || !entry->refcount) {
|
||||
mlx5_core_warn(dev, "Rate %u, max_burst_sz %u typical_pkt_sz %u are not configured\n",
|
||||
rl->rate, rl->max_burst_sz, rl->typical_pkt_sz);
|
||||
@ -223,11 +292,9 @@ void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl)
|
||||
}
|
||||
|
||||
entry->refcount--;
|
||||
if (!entry->refcount) {
|
||||
if (!entry->refcount)
|
||||
/* need to remove rate */
|
||||
mlx5_set_pp_rate_limit_cmd(dev, entry->index, &reset_rl);
|
||||
entry->rl = reset_rl;
|
||||
}
|
||||
mlx5_set_pp_rate_limit_cmd(dev, entry, false);
|
||||
|
||||
out:
|
||||
mutex_unlock(&table->rl_lock);
|
||||
@ -273,14 +340,13 @@ int mlx5_init_rl_table(struct mlx5_core_dev *dev)
|
||||
void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev)
|
||||
{
|
||||
struct mlx5_rl_table *table = &dev->priv.rl_table;
|
||||
struct mlx5_rate_limit rl = {0};
|
||||
int i;
|
||||
|
||||
/* Clear all configured rates */
|
||||
for (i = 0; i < table->max_size; i++)
|
||||
if (table->rl_entry[i].rl.rate)
|
||||
mlx5_set_pp_rate_limit_cmd(dev, table->rl_entry[i].index,
|
||||
&rl);
|
||||
if (table->rl_entry[i].refcount)
|
||||
mlx5_set_pp_rate_limit_cmd(dev, &table->rl_entry[i],
|
||||
false);
|
||||
|
||||
kfree(dev->priv.rl_table.rl_entry);
|
||||
}
|
||||
|
@ -518,9 +518,11 @@ struct mlx5_rate_limit {
|
||||
};
|
||||
|
||||
struct mlx5_rl_entry {
|
||||
struct mlx5_rate_limit rl;
|
||||
u16 index;
|
||||
u16 refcount;
|
||||
u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
|
||||
u16 index;
|
||||
u64 refcount;
|
||||
u16 uid;
|
||||
u8 dedicated : 1;
|
||||
};
|
||||
|
||||
struct mlx5_rl_table {
|
||||
@ -1007,6 +1009,9 @@ int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
|
||||
struct mlx5_rate_limit *rl);
|
||||
void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
|
||||
bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
|
||||
int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
|
||||
bool dedicated_entry, u16 *index);
|
||||
void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
|
||||
bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
|
||||
struct mlx5_rate_limit *rl_1);
|
||||
int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
|
||||
|
@ -813,7 +813,9 @@ struct mlx5_ifc_qos_cap_bits {
|
||||
u8 reserved_at_4[0x1];
|
||||
u8 packet_pacing_burst_bound[0x1];
|
||||
u8 packet_pacing_typical_size[0x1];
|
||||
u8 reserved_at_7[0x19];
|
||||
u8 reserved_at_7[0x4];
|
||||
u8 packet_pacing_uid[0x1];
|
||||
u8 reserved_at_c[0x14];
|
||||
|
||||
u8 reserved_at_20[0x20];
|
||||
|
||||
@ -8265,9 +8267,20 @@ struct mlx5_ifc_set_pp_rate_limit_out_bits {
|
||||
u8 reserved_at_40[0x40];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_set_pp_rate_limit_context_bits {
|
||||
u8 rate_limit[0x20];
|
||||
|
||||
u8 burst_upper_bound[0x20];
|
||||
|
||||
u8 reserved_at_40[0x10];
|
||||
u8 typical_packet_size[0x10];
|
||||
|
||||
u8 reserved_at_60[0x120];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_set_pp_rate_limit_in_bits {
|
||||
u8 opcode[0x10];
|
||||
u8 reserved_at_10[0x10];
|
||||
u8 uid[0x10];
|
||||
|
||||
u8 reserved_at_20[0x10];
|
||||
u8 op_mod[0x10];
|
||||
@ -8277,14 +8290,7 @@ struct mlx5_ifc_set_pp_rate_limit_in_bits {
|
||||
|
||||
u8 reserved_at_60[0x20];
|
||||
|
||||
u8 rate_limit[0x20];
|
||||
|
||||
u8 burst_upper_bound[0x20];
|
||||
|
||||
u8 reserved_at_c0[0x10];
|
||||
u8 typical_packet_size[0x10];
|
||||
|
||||
u8 reserved_at_e0[0x120];
|
||||
struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
|
||||
};
|
||||
|
||||
struct mlx5_ifc_access_register_out_bits {
|
||||
|
@ -608,7 +608,7 @@ struct mlx5_ifc_tls_cmd_bits {
|
||||
struct mlx5_ifc_tls_resp_bits {
|
||||
u8 syndrome[0x20];
|
||||
u8 stream_id[0x20];
|
||||
u8 reserverd[0x40];
|
||||
u8 reserved[0x40];
|
||||
};
|
||||
|
||||
#define MLX5_TLS_COMMAND_SIZE (0x100)
|
||||
|
@ -143,6 +143,22 @@ enum mlx5_ib_devx_umem_dereg_attrs {
|
||||
MLX5_IB_ATTR_DEVX_UMEM_DEREG_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
|
||||
};
|
||||
|
||||
enum mlx5_ib_pp_obj_methods {
|
||||
MLX5_IB_METHOD_PP_OBJ_ALLOC = (1U << UVERBS_ID_NS_SHIFT),
|
||||
MLX5_IB_METHOD_PP_OBJ_DESTROY,
|
||||
};
|
||||
|
||||
enum mlx5_ib_pp_alloc_attrs {
|
||||
MLX5_IB_ATTR_PP_OBJ_ALLOC_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
|
||||
MLX5_IB_ATTR_PP_OBJ_ALLOC_CTX,
|
||||
MLX5_IB_ATTR_PP_OBJ_ALLOC_FLAGS,
|
||||
MLX5_IB_ATTR_PP_OBJ_ALLOC_INDEX,
|
||||
};
|
||||
|
||||
enum mlx5_ib_pp_obj_destroy_attrs {
|
||||
MLX5_IB_ATTR_PP_OBJ_DESTROY_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
|
||||
};
|
||||
|
||||
enum mlx5_ib_devx_umem_methods {
|
||||
MLX5_IB_METHOD_DEVX_UMEM_REG = (1U << UVERBS_ID_NS_SHIFT),
|
||||
MLX5_IB_METHOD_DEVX_UMEM_DEREG,
|
||||
@ -173,6 +189,7 @@ enum mlx5_ib_objects {
|
||||
MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD,
|
||||
MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD,
|
||||
MLX5_IB_OBJECT_VAR,
|
||||
MLX5_IB_OBJECT_PP,
|
||||
};
|
||||
|
||||
enum mlx5_ib_flow_matcher_create_attrs {
|
||||
|
@ -73,5 +73,9 @@ struct mlx5_ib_uapi_devx_async_event_hdr {
|
||||
__u8 out_data[];
|
||||
};
|
||||
|
||||
enum mlx5_ib_uapi_pp_alloc_flags {
|
||||
MLX5_IB_UAPI_PP_ALLOC_FLAGS_DEDICATED_INDEX = 1 << 0,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user