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drm/amdgpu/display: switch udelay to msleep

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We may need to sleep for up to 80ms
(8ms per each of up to 10 loop iterations):

/* First DPCD read after VDD ON can fail if the particular board
 * does not have HPD pin wired correctly. So if DPCD read fails,
 * which it should never happen, retry a few times. Target worst
 * case scenario of 80 ms.
 */

Switch udelay to msleep to avoid limits on arm.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2019-06-25 08:54:21 -05:00
parent 44ff0ae6b1
commit 3e10f3196b
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/core/dc_link.c
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@ -550,7 +550,7 @@ static void read_edp_current_link_settings_on_detect(struct dc_link *link)
break;
}
udelay(8000);
msleep(8);
}
ASSERT(status == DC_OK);