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KVM: arm/arm64: vgic-v3: Do not use Active+Pending state for a HW interrupt

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When an interrupt is injected with the HW bit set (indicating that
deactivation should be propagated to the physical distributor),
special care must be taken so that we never mark the corresponding
LR with the Active+Pending state (as the pending state is kept in
the physycal distributor).

Cc: stable@vger.kernel.org
Fixes: 59529f69f5 ("KVM: arm/arm64: vgic-new: Add GICv3 world switch backend")
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
This commit is contained in:
Marc Zyngier 2017-05-02 14:30:40 +01:00 committed by Christoffer Dall
parent ddf42d068f
commit 3d6e77ad14
1 changed files with 7 additions and 0 deletions
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7
virt/kvm/arm/vgic/vgic-v3.c
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@ -127,6 +127,13 @@ void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
if (irq->hw) { if (irq->hw) {
val |= ICH_LR_HW; val |= ICH_LR_HW;
val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT; val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
/*
* Never set pending+active on a HW interrupt, as the
* pending state is kept at the physical distributor
* level.
*/
if (irq->active && irq_is_pending(irq))
val &= ~ICH_LR_PENDING_BIT;
} else { } else {
if (irq->config == VGIC_CONFIG_LEVEL) if (irq->config == VGIC_CONFIG_LEVEL)
val |= ICH_LR_EOI; val |= ICH_LR_EOI;