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TI clock driver changes for v4.20 merge window.

Browse Source 
This tag adds changes for the Texas Instruments clock driver. Included
 changes are:
 - clkctrl driver changes switching the layout from CM based to clockdomain
   based. Needed for ongoing hwmod transition towards sysc driver. Changed
   SoCs for this include am3,am4,am5,dra7.
 - RTC+DDR sleep mode support code for clock save/restore. The deep sleep
   states will wipe the clock register space on the SoC, requiring save/
   restore support so that the state can be retained over the sleep state.
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Merge tag 'clk-ti-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into clk-ti

Pull TI clock driver updates from Tero Kristo:

This tag adds changes for the Texas Instruments clock driver. Included
changes are:
- clkctrl driver changes switching the layout from CM based to clockdomain
  based. Needed for ongoing hwmod transition towards sysc driver. Changed
  SoCs for this include am3,am4,am5,dra7.
- RTC+DDR sleep mode support code for clock save/restore. The deep sleep
  states will wipe the clock register space on the SoC, requiring save/
  restore support so that the state can be retained over the sleep state.

* tag 'clk-ti-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
  clk: ti: Add functions to save/restore clk context
  clk: clk: Add clk_gate_restore_context function
  clk: Add functions to save/restore clock context en-masse
  clk: ti: dra7: add new clkctrl data
  clk: ti: dra7xx: rename existing clkctrl data as compat data
  clk: ti: am43xx: add new clkctrl data for am43xx
  clk: ti: am43xx: rename existing clkctrl data as compat data
  clk: ti: am33xx: add new clkctrl data for am33xx
  clk: ti: am33xx: rename existing clkctrl data as compat data
  clk: ti: clkctrl: replace dashes from clkdm name with underscore
  clk: ti: clkctrl: support multiple clkctrl nodes under a cm node
  dt-bindings: clock: dra7xx: add clkctrl indices for new data layout
  dt-bindings: clock: am43xx: add clkctrl indices for new data layout
  dt-bindings: clock: am33xx: add clkctrl indices for new data layout
  clk: ti: fix OF child-node lookup
This commit is contained in:
Stephen Boyd 2018-10-11 00:22:55 -07:00
commit 3d30622143
22 changed files with 2839 additions and 557 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

93
drivers/clk/clk.c
View File

@ -923,6 +923,99 @@ static int clk_core_enable_lock(struct clk_core *core)
return ret;
}
/**
* clk_gate_restore_context - restore context for poweroff
* @hw: the clk_hw pointer of clock whose state is to be restored
*
* The clock gate restore context function enables or disables
* the gate clocks based on the enable_count. This is done in cases
* where the clock context is lost and based on the enable_count
* the clock either needs to be enabled/disabled. This
* helps restore the state of gate clocks.
*/
void clk_gate_restore_context(struct clk_hw *hw)
{
if (hw->clk->core->enable_count)
hw->clk->core->ops->enable(hw);
else
hw->clk->core->ops->disable(hw);
}
EXPORT_SYMBOL_GPL(clk_gate_restore_context);
static int _clk_save_context(struct clk_core *clk)
{
struct clk_core *child;
int ret = 0;
hlist_for_each_entry(child, &clk->children, child_node) {
ret = _clk_save_context(child);
if (ret < 0)
return ret;
}
if (clk->ops && clk->ops->save_context)
ret = clk->ops->save_context(clk->hw);
return ret;
}
static void _clk_restore_context(struct clk_core *clk)
{
struct clk_core *child;
if (clk->ops && clk->ops->restore_context)
clk->ops->restore_context(clk->hw);
hlist_for_each_entry(child, &clk->children, child_node)
_clk_restore_context(child);
}
/**
* clk_save_context - save clock context for poweroff
*
* Saves the context of the clock register for powerstates in which the
* contents of the registers will be lost. Occurs deep within the suspend
* code. Returns 0 on success.
*/
int clk_save_context(void)
{
struct clk_core *clk;
int ret;
hlist_for_each_entry(clk, &clk_root_list, child_node) {
ret = _clk_save_context(clk);
if (ret < 0)
return ret;
}
hlist_for_each_entry(clk, &clk_orphan_list, child_node) {
ret = _clk_save_context(clk);
if (ret < 0)
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(clk_save_context);
/**
* clk_restore_context - restore clock context after poweroff
*
* Restore the saved clock context upon resume.
*
*/
void clk_restore_context(void)
{
struct clk_core *clk;
hlist_for_each_entry(clk, &clk_root_list, child_node)
_clk_restore_context(clk);
hlist_for_each_entry(clk, &clk_orphan_list, child_node)
_clk_restore_context(clk);
}
EXPORT_SYMBOL_GPL(clk_restore_context);
/**
* clk_enable - ungate a clock
* @clk: the clk being ungated

9
drivers/clk/ti/Makefile
View File

@ -6,7 +6,8 @@ clk-common = dpll.o composite.o divider.o gate.o \
fixed-factor.o mux.o apll.o \
clkt_dpll.o clkt_iclk.o clkt_dflt.o \
clkctrl.o
obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o
obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o \
clk-33xx-compat.o
obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o
obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
@ -16,8 +17,10 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o \
obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \
dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
clk-dra7-atl.o dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o
clk-dra7-atl.o dpll3xxx.o \
dpll44xx.o clk-7xx-compat.o
obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o \
clk-43xx-compat.o
endif # CONFIG_ARCH_OMAP2PLUS

218
drivers/clk/ti/clk-33xx-compat.c Normal file
View File

@ -0,0 +1,218 @@
/*
* AM33XX Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc
* Tero Kristo (t-kristo@ti.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/am3.h>
#include "clock.h"
static const char * const am3_gpio1_dbclk_parents[] __initconst = {
"l4_per_cm:clk:0138:0",
NULL,
};
static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
{ AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
{ AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },
{ AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
{ AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
{ AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
{ AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
{ AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
{ AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
{ AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
{ AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
{ AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
{ AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
{ AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
{ AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
{ AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
{ AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
{ AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
{ AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
{ AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
{ AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
{ AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
{ 0 },
};
static const char * const am3_gpio0_dbclk_parents[] __initconst = {
"gpio0_dbclk_mux_ck",
NULL,
};
static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
{ 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
{ 0 },
};
static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
"sys_clkin_ck",
NULL,
};
static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
"l4_wkup_cm:clk:0010:19",
"l4_wkup_cm:clk:0010:30",
NULL,
};
static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
"l4_wkup_cm:clk:0010:20",
NULL,
};
static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
.max_div = 64,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
"l4_wkup_cm:clk:0010:22",
NULL,
};
static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
.max_div = 64,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const char * const am3_dbg_clka_ck_parents[] __initconst = {
"dpll_core_m4_ck",
NULL,
};
static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
{ 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
{ 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
{ 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
{ 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
{ 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
{ 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
{ AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
{ AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
{ AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
{ AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
{ AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
{ AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
{ AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
{ AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
{ AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
{ AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
{ AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
{ AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
{ AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
{ AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
{ AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
{ AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
{ 0 },
};
const struct omap_clkctrl_data am3_clkctrl_compat_data[] __initconst = {
{ 0x44e00014, am3_l4_per_clkctrl_regs },
{ 0x44e00404, am3_l4_wkup_clkctrl_regs },
{ 0x44e00604, am3_mpu_clkctrl_regs },
{ 0x44e00800, am3_l4_rtc_clkctrl_regs },
{ 0x44e00904, am3_gfx_l3_clkctrl_regs },
{ 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
{ 0 },
};
struct ti_dt_clk am33xx_compat_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
{ .node_name = NULL },
};

232
drivers/clk/ti/clk-33xx.c
View File

@ -24,7 +24,7 @@
#include "clock.h"
static const char * const am3_gpio1_dbclk_parents[] __initconst = {
"l4_per_cm:clk:0138:0",
"clk-24mhz-clkctrl:0000:0",
NULL,
};
@ -43,58 +43,86 @@ static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
{ AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
{ AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },
{ AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
{ AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
{ AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
{ AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
{ AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
{ AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
{ AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
{ AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
{ AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
{ AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
{ AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
{ AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
{ AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
{ AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
{ AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
{ AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
{ AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
{ AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
{ AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = {
{ AM3_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM3_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
{ AM3_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
{ AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
{ AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
{ AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
{ AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
{ AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
{ AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
{ AM3_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
{ AM3_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM3_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l3s_clkctrl_regs[] __initconst = {
{ AM3_L3S_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck" },
{ AM3_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
{ AM3_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
{ AM3_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
{ AM3_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l3_clkctrl_regs[] __initconst = {
{ AM3_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck" },
{ AM3_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
{ AM3_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = {
{ AM3_L4HS_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = {
{ AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_cpsw_125mhz_clkctrl_regs[] __initconst = {
{ AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_lcdc_clkctrl_regs[] __initconst = {
{ AM3_LCDC_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_clk_24mhz_clkctrl_regs[] __initconst = {
{ AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck" },
{ 0 },
};
@ -108,19 +136,33 @@ static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
{ AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
{ AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
{ AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
{ AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
{ AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
{ AM3_L4_WKUP_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
{ AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
{ AM3_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
{ AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
{ AM3_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
{ 0 },
};
static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
"sys_clkin_ck",
NULL,
};
static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
"l4_wkup_cm:clk:0010:19",
"l4_wkup_cm:clk:0010:30",
"l3-aon-clkctrl:0000:19",
"l3-aon-clkctrl:0000:30",
NULL,
};
static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
"l4_wkup_cm:clk:0010:20",
"l3-aon-clkctrl:0000:20",
NULL,
};
@ -130,7 +172,7 @@ static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst
};
static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
"l4_wkup_cm:clk:0010:22",
"l3-aon-clkctrl:0000:22",
NULL,
};
@ -154,66 +196,69 @@ static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
{ AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
{ AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
{ AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
{ AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
{ AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
{ AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
{ AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
{ AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
{ AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
{ AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
{ AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
{ AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
static const struct omap_clkctrl_reg_data am3_l3_aon_clkctrl_regs[] __initconst = {
{ AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_wkup_aon_clkctrl_regs[] __initconst = {
{ AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
{ AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
{ AM3_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
{ AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
{ AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
{ AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
{ AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
{ AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
{ AM3_L4_CEFUSE_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
{ 0 },
};
const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
{ 0x44e00014, am3_l4_per_clkctrl_regs },
{ 0x44e00404, am3_l4_wkup_clkctrl_regs },
{ 0x44e00604, am3_mpu_clkctrl_regs },
{ 0x44e00038, am3_l4ls_clkctrl_regs },
{ 0x44e0001c, am3_l3s_clkctrl_regs },
{ 0x44e00024, am3_l3_clkctrl_regs },
{ 0x44e00120, am3_l4hs_clkctrl_regs },
{ 0x44e000e8, am3_pruss_ocp_clkctrl_regs },
{ 0x44e00000, am3_cpsw_125mhz_clkctrl_regs },
{ 0x44e00018, am3_lcdc_clkctrl_regs },
{ 0x44e0014c, am3_clk_24mhz_clkctrl_regs },
{ 0x44e00400, am3_l4_wkup_clkctrl_regs },
{ 0x44e00414, am3_l3_aon_clkctrl_regs },
{ 0x44e004b0, am3_l4_wkup_aon_clkctrl_regs },
{ 0x44e00600, am3_mpu_clkctrl_regs },
{ 0x44e00800, am3_l4_rtc_clkctrl_regs },
{ 0x44e00904, am3_gfx_l3_clkctrl_regs },
{ 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
{ 0x44e00900, am3_gfx_l3_clkctrl_regs },
{ 0x44e00a00, am3_l4_cefuse_clkctrl_regs },
{ 0 },
};
static struct ti_dt_clk am33xx_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0008:18"),
DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0074:18"),
DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0078:18"),
DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:007c:18"),
DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l3-aon-clkctrl:0000:20"),
{ .node_name = NULL },
};
@ -232,7 +277,10 @@ int __init am33xx_dt_clk_init(void)
{
struct clk *clk1, *clk2;
ti_dt_clocks_register(am33xx_clks);
if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
ti_dt_clocks_register(am33xx_compat_clks);
else
ti_dt_clocks_register(am33xx_clks);
omap2_clk_disable_autoidle_all();

225
drivers/clk/ti/clk-43xx-compat.c Normal file
View File

@ -0,0 +1,225 @@
/*
* AM43XX Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc
* Tero Kristo (t-kristo@ti.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/am4.h>
#include "clock.h"
static const char * const am4_synctimer_32kclk_parents[] __initconst = {
"mux_synctimer32k_ck",
NULL,
};
static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
{ 0 },
};
static const char * const am4_gpio0_dbclk_parents[] __initconst = {
"gpio0_dbclk_mux_ck",
NULL,
};
static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
{ AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" },
{ AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
{ AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" },
{ AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" },
{ AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" },
{ AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" },
{ AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
{ AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
{ AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" },
{ AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
{ AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
{ AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
{ AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
{ AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
{ AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
{ 0 },
};
static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
"dpll_per_clkdcoldo",
NULL,
};
static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
{ 0 },
};
static const char * const am4_gpio1_dbclk_parents[] __initconst = {
"clkdiv32k_ick",
NULL,
};
static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = {
{ AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
{ AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
{ AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
{ AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" },
{ AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
{ AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
{ AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
{ AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
{ AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
{ AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
{ AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
{ AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
{ AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
{ AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
{ AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
{ AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
{ AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
{ AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
{ AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
{ AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
{ AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
{ AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
{ AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
{ AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
{ AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
{ AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
{ AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
{ AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" },
{ AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
{ 0 },
};
const struct omap_clkctrl_data am4_clkctrl_compat_data[] __initconst = {
{ 0x44df2820, am4_l4_wkup_clkctrl_regs },
{ 0x44df8320, am4_mpu_clkctrl_regs },
{ 0x44df8420, am4_gfx_l3_clkctrl_regs },
{ 0x44df8520, am4_l4_rtc_clkctrl_regs },
{ 0x44df8820, am4_l4_per_clkctrl_regs },
{ 0 },
};
const struct omap_clkctrl_data am438x_clkctrl_compat_data[] __initconst = {
{ 0x44df2820, am4_l4_wkup_clkctrl_regs },
{ 0x44df8320, am4_mpu_clkctrl_regs },
{ 0x44df8420, am4_gfx_l3_clkctrl_regs },
{ 0x44df8820, am4_l4_per_clkctrl_regs },
{ 0 },
};
struct ti_dt_clk am43xx_compat_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"),
DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"),
DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"),
DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"),
DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"),
DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"),
DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"),
DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"),
DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"),
{ .node_name = NULL },
};

249
drivers/clk/ti/clk-43xx.c
View File

@ -23,6 +23,11 @@
#include "clock.h"
static const struct omap_clkctrl_reg_data am4_l3s_tsc_clkctrl_regs[] __initconst = {
{ AM4_L3S_TSC_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
{ 0 },
};
static const char * const am4_synctimer_32kclk_parents[] __initconst = {
"mux_synctimer32k_ck",
NULL,
@ -33,6 +38,12 @@ static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l4_wkup_aon_clkctrl_regs[] __initconst = {
{ AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sys_clkin_ck" },
{ AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl:0008:8" },
{ 0 },
};
static const char * const am4_gpio0_dbclk_parents[] __initconst = {
"gpio0_dbclk_mux_ck",
NULL,
@ -44,33 +55,45 @@ static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
};
static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
{ AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" },
{ AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
{ AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" },
{ AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" },
{ AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" },
{ AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" },
{ AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
{ AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
{ AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" },
{ AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
{ AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
{ AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
{ AM4_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
{ AM4_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
{ AM4_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
{ AM4_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
{ AM4_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
{ AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
{ AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
{ AM4_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
{ AM4_L4_WKUP_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
{ AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
{ AM4_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
{ AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
{ AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
{ AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
{ AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l3_clkctrl_regs[] __initconst = {
{ AM4_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
{ AM4_L3_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
{ 0 },
};
@ -89,6 +112,24 @@ static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l3s_clkctrl_regs[] __initconst = {
{ AM4_L3S_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3S_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
{ AM4_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
{ AM4_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
{ AM4_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM4_L3S_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
{ AM4_L3S_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk" },
{ AM4_L3S_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_pruss_ocp_clkctrl_regs[] __initconst = {
{ AM4_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk" },
{ 0 },
};
static const char * const am4_gpio1_dbclk_parents[] __initconst = {
"clkdiv32k_ick",
NULL,
@ -119,108 +160,115 @@ static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = {
{ AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
{ AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
{ AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
{ AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" },
{ AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
{ AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
{ AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
{ AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
{ AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
{ AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
{ AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
{ AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
{ AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
{ AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
{ AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
{ AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
{ AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
{ AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
{ AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
{ AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
{ AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
{ AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
{ AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
{ AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
{ AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
{ AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
{ AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
{ AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" },
{ AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
static const struct omap_clkctrl_reg_data am4_l4ls_clkctrl_regs[] __initconst = {
{ AM4_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
{ AM4_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
{ AM4_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
{ AM4_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM4_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM4_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
{ AM4_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
{ AM4_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
{ AM4_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
{ AM4_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
{ AM4_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
{ AM4_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
{ AM4_L4LS_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
{ AM4_L4LS_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
{ AM4_L4LS_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
{ AM4_L4LS_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
{ AM4_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_emif_clkctrl_regs[] __initconst = {
{ AM4_EMIF_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_dss_clkctrl_regs[] __initconst = {
{ AM4_DSS_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_cpsw_125mhz_clkctrl_regs[] __initconst = {
{ AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
{ 0 },
};
const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
{ 0x44df2820, am4_l4_wkup_clkctrl_regs },
{ 0x44df2920, am4_l3s_tsc_clkctrl_regs },
{ 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
{ 0x44df2a20, am4_l4_wkup_clkctrl_regs },
{ 0x44df8320, am4_mpu_clkctrl_regs },
{ 0x44df8420, am4_gfx_l3_clkctrl_regs },
{ 0x44df8520, am4_l4_rtc_clkctrl_regs },
{ 0x44df8820, am4_l4_per_clkctrl_regs },
{ 0x44df8820, am4_l3_clkctrl_regs },
{ 0x44df8868, am4_l3s_clkctrl_regs },
{ 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
{ 0x44df8c20, am4_l4ls_clkctrl_regs },
{ 0x44df8f20, am4_emif_clkctrl_regs },
{ 0x44df9220, am4_dss_clkctrl_regs },
{ 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
{ 0 },
};
const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = {
{ 0x44df2820, am4_l4_wkup_clkctrl_regs },
{ 0x44df2920, am4_l3s_tsc_clkctrl_regs },
{ 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
{ 0x44df2a20, am4_l4_wkup_clkctrl_regs },
{ 0x44df8320, am4_mpu_clkctrl_regs },
{ 0x44df8420, am4_gfx_l3_clkctrl_regs },
{ 0x44df8820, am4_l4_per_clkctrl_regs },
{ 0x44df8820, am4_l3_clkctrl_regs },
{ 0x44df8868, am4_l3s_clkctrl_regs },
{ 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
{ 0x44df8c20, am4_l4ls_clkctrl_regs },
{ 0x44df8f20, am4_emif_clkctrl_regs },
{ 0x44df9220, am4_dss_clkctrl_regs },
{ 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
{ 0 },
};
static struct ti_dt_clk am43xx_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"),
DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"),
DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"),
DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"),
DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"),
DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"),
DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"),
DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"),
DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"),
DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"),
DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"),
DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"),
DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"),
DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"),
DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"),
DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"),
DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"),
DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"),
{ .node_name = NULL },
};
@ -228,7 +276,10 @@ int __init am43xx_dt_clk_init(void)
{
struct clk *clk1, *clk2;
ti_dt_clocks_register(am43xx_clks);
if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
ti_dt_clocks_register(am43xx_compat_clks);
else
ti_dt_clocks_register(am43xx_clks);
omap2_clk_disable_autoidle_all();

823
drivers/clk/ti/clk-7xx-compat.c Normal file
View File

@ -0,0 +1,823 @@
/*
* DRA7 Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo (t-kristo@ti.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/dra7.h>
#include "clock.h"
#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
#define DRA7_DPLL_USB_DEFFREQ 960000000
static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
{ DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
{ 0 },
};
static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
"per_abe_x1_gfclk2_div",
"video1_clk2_div",
"video2_clk2_div",
"hdmi_clk2_div",
NULL,
};
static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
"abe_24m_fclk",
"abe_sys_clk_div",
"func_24m_clk",
"atl_clkin3_ck",
"atl_clkin2_ck",
"atl_clkin1_ck",
"atl_clkin0_ck",
"sys_clkin2",
"ref_clkin0_ck",
"ref_clkin1_ck",
"ref_clkin2_ck",
"ref_clkin3_ck",
"mlb_clk",
"mlbp_clk",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
"timer_sys_clk_div",
"sys_32k_ck",
"sys_clkin2",
"ref_clkin0_ck",
"ref_clkin1_ck",
"ref_clkin2_ck",
"ref_clkin3_ck",
"abe_giclk_div",
"video1_div_clk",
"video2_div_clk",
"hdmi_div_clk",
"clkoutmux0_clk_mux",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
"func_48m_fclk",
"dpll_per_m2x2_ck",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
{ DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
{ DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
{ DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
{ DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
{ DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
{ DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
{ DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
{ DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
{ DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
{ DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
{ DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
{ DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
"sys_32k_ck",
"video1_clkin_ck",
"video2_clkin_ck",
"hdmi_clkin_ck",
NULL,
};
static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
"l3_iclk_div",
"dpll_abe_m2_ck",
"atl_cm:clk:0000:24",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
{ 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
{ DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
{ DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
{ DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ 0 },
};
static const char * const dra7_dss_dss_clk_parents[] __initconst = {
"dpll_per_h12x2_ck",
NULL,
};
static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
"func_48m_fclk",
NULL,
};
static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
"hdmi_dpll_clk_mux",
NULL,
};
static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
"sys_32k_ck",
NULL,
};
static const char * const dra7_dss_video1_clk_parents[] __initconst = {
"video1_dpll_clk_mux",
NULL,
};
static const char * const dra7_dss_video2_clk_parents[] __initconst = {
"video2_dpll_clk_mux",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
{ 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
{ 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
{ 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
{ 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
{ DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
{ DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
{ 0 },
};
static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
"func_128m_clk",
"dpll_per_m2x2_ck",
NULL,
};
static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
"l3init_cm:clk:0008:24",
NULL,
};
static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
{ 0 },
};
static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
"l3init_cm:clk:0010:24",
NULL,
};
static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
{ 0 },
};
static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
"l3init_960m_gfclk",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
{ 0 },
};
static const char * const dra7_sata_ref_clk_parents[] __initconst = {
"sys_clkin1",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
{ 0 },
};
static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
"apll_pcie_ck",
NULL,
};
static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
"optfclk_pciephy_div",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
{ 0 },
};
static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
"dpll_gmac_h11x2_ck",
"rmii_clk_ck",
NULL,
};
static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
"video1_clkin_ck",
"video2_clkin_ck",
"dpll_abe_m2_ck",
"hdmi_clkin_ck",
"l3_iclk_div",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
{ 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
{ DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
{ DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
{ DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
{ DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
{ DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
{ DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ 0 },
};
static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
"timer_sys_clk_div",
"sys_32k_ck",
"sys_clkin2",
"ref_clkin0_ck",
"ref_clkin1_ck",
"ref_clkin2_ck",
"ref_clkin3_ck",
"abe_giclk_div",
"video1_div_clk",
"video2_div_clk",
"hdmi_div_clk",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
"l4per_cm:clk:0120:24",
NULL,
};
static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
{ 0 },
};
static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
"l4per_cm:clk:0128:24",
NULL,
};
static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
"func_128m_clk",
"dpll_per_h13x2_ck",
NULL,
};
static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
"l4per_cm:clk:0138:24",
NULL,
};
static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
{ DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
{ DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
{ DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
{ DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
{ DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
{ DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
{ DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
{ DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
{ DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
{ DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
{ DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
{ DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
{ DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
{ DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
{ DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
{ DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
{ DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
{ DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
{ DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
{ DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
{ DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
{ DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
{ DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
{ DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
{ DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
{ DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
{ DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
{ DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
{ DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
{ DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
{ DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
{ DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
{ DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
{ DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
{ DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
{ DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
{ DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
{ DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
{ DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
{ DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
"sys_clkin1",
"sys_clkin2",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
{ DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
{ DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
{ DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
{ DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
{ DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
{ DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"},
{ 0 },
};
const struct omap_clkctrl_data dra7_clkctrl_compat_data[] __initconst = {
{ 0x4a005320, dra7_mpu_clkctrl_regs },
{ 0x4a005540, dra7_ipu_clkctrl_regs },
{ 0x4a005740, dra7_rtc_clkctrl_regs },
{ 0x4a008620, dra7_coreaon_clkctrl_regs },
{ 0x4a008720, dra7_l3main1_clkctrl_regs },
{ 0x4a008a20, dra7_dma_clkctrl_regs },
{ 0x4a008b20, dra7_emif_clkctrl_regs },
{ 0x4a008c00, dra7_atl_clkctrl_regs },
{ 0x4a008d20, dra7_l4cfg_clkctrl_regs },
{ 0x4a008e20, dra7_l3instr_clkctrl_regs },
{ 0x4a009120, dra7_dss_clkctrl_regs },
{ 0x4a009320, dra7_l3init_clkctrl_regs },
{ 0x4a009700, dra7_l4per_clkctrl_regs },
{ 0x4ae07820, dra7_wkupaon_clkctrl_regs },
{ 0 },
};
struct ti_dt_clk dra7xx_compat_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
{ .node_name = NULL },
};

598
drivers/clk/ti/clk-7xx.c
View File

@ -23,7 +23,28 @@
#define DRA7_DPLL_USB_DEFFREQ 960000000
static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
{ DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
{ DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
{ DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" },
{ 0 },
};
static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
"dpll_abe_m2x2_ck",
"dpll_core_h22x2_ck",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
{ DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP, "ipu1-clkctrl:0000:24" },
{ 0 },
};
@ -108,45 +129,55 @@ static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
};
static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
{ DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
{ DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
{ DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
{ DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
{ DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
{ DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
{ DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
{ DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
{ DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
{ DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
{ DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
{ DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
{ DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
{ DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
{ DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
{ DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
{ DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
{ DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
{ DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
{ DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
{ DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
{ DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
@ -161,7 +192,7 @@ static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
"l3_iclk_div",
"dpll_abe_m2_ck",
"atl_cm:clk:0000:24",
"atl-clkctrl:0000:24",
NULL,
};
@ -172,32 +203,32 @@ static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
};
static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
{ DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
{ DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
{ DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
{ DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ 0 },
};
@ -242,8 +273,8 @@ static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst =
};
static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
{ DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
{ DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
{ DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
{ DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
{ 0 },
};
@ -254,7 +285,7 @@ static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
};
static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
"l3init_cm:clk:0008:24",
"l3init-clkctrl:0008:24",
NULL,
};
@ -271,7 +302,7 @@ static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
};
static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
"l3init_cm:clk:0010:24",
"l3init-clkctrl:0010:24",
NULL,
};
@ -307,6 +338,24 @@ static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
{ DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
{ DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
{ DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ 0 },
};
static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
"apll_pcie_ck",
NULL,
@ -331,6 +380,12 @@ static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {
{ DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
{ DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
{ 0 },
};
static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
"dpll_gmac_h11x2_ck",
"rmii_clk_ck",
@ -352,24 +407,8 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
{ DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
{ DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
{ DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
{ DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
{ DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
{ DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
{ DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" },
{ 0 },
};
@ -443,21 +482,6 @@ static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
@ -469,7 +493,7 @@ static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
};
static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
"l4per_cm:clk:0120:24",
"l4per-clkctrl:00f8:24",
NULL,
};
@ -486,7 +510,7 @@ static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
};
static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
"l4per_cm:clk:0128:24",
"l4per-clkctrl:0100:24",
NULL,
};
@ -502,33 +526,6 @@ static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
"func_128m_clk",
"dpll_per_h13x2_ck",
NULL,
};
static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
"l4per_cm:clk:0138:24",
NULL,
};
static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
@ -549,6 +546,77 @@ static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
{ DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" },
{ DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
{ DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
{ DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
{ DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
{ DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
{ DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
{ DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" },
{ DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" },
{ DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" },
{ DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" },
{ DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" },
{ DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" },
{ DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {
{ DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "" },
{ DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ 0 },
};
static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
"func_128m_clk",
"dpll_per_h13x2_ck",
NULL,
};
static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
"l4per2-clkctrl:012c:24",
NULL,
};
static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
@ -562,11 +630,6 @@ static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
@ -612,64 +675,54 @@ static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
{ DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
{ DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
{ DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
{ DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
{ DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
{ DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
{ DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
{ DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
{ DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
{ DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
{ DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
{ DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
{ DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
{ DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
{ DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
{ DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
{ DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
{ DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
{ DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
{ DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
{ DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
{ DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
{ DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
{ DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
{ DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
{ DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
{ DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
{ DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
{ DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
{ DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
{ DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
{ DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
{ DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
{ DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
{ DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
{ DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
{ DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
{ DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
{ DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
{ DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {
{ DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
{ DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
{ DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
{ DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" },
{ DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
{ DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
{ DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" },
{ DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
{ DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
{ DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
{ DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" },
{ DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },
{ DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },
{ DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {
{ DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" },
{ DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" },
{ DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" },
{ DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" },
{ 0 },
};
@ -700,24 +753,28 @@ static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
};
static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
{ DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
{ DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
{ DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
{ DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
{ DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
{ DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"},
{ DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
{ DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
{ DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
{ DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
{ DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
{ DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk" },
{ 0 },
};
const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
{ 0x4a005320, dra7_mpu_clkctrl_regs },
{ 0x4a005540, dra7_ipu_clkctrl_regs },
{ 0x4a005740, dra7_rtc_clkctrl_regs },
{ 0x4a005420, dra7_dsp1_clkctrl_regs },
{ 0x4a005520, dra7_ipu1_clkctrl_regs },
{ 0x4a005550, dra7_ipu_clkctrl_regs },
{ 0x4a005620, dra7_dsp2_clkctrl_regs },
{ 0x4a005720, dra7_rtc_clkctrl_regs },
{ 0x4a008620, dra7_coreaon_clkctrl_regs },
{ 0x4a008720, dra7_l3main1_clkctrl_regs },
{ 0x4a008920, dra7_ipu2_clkctrl_regs },
{ 0x4a008a20, dra7_dma_clkctrl_regs },
{ 0x4a008b20, dra7_emif_clkctrl_regs },
{ 0x4a008c00, dra7_atl_clkctrl_regs },
@ -725,7 +782,12 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
{ 0x4a008e20, dra7_l3instr_clkctrl_regs },
{ 0x4a009120, dra7_dss_clkctrl_regs },
{ 0x4a009320, dra7_l3init_clkctrl_regs },
{ 0x4a009700, dra7_l4per_clkctrl_regs },
{ 0x4a0093b0, dra7_pcie_clkctrl_regs },
{ 0x4a0093d0, dra7_gmac_clkctrl_regs },
{ 0x4a009728, dra7_l4per_clkctrl_regs },
{ 0x4a0098a0, dra7_l4sec_clkctrl_regs },
{ 0x4a00970c, dra7_l4per2_clkctrl_regs },
{ 0x4a009714, dra7_l4per3_clkctrl_regs },
{ 0x4ae07820, dra7_wkupaon_clkctrl_regs },
{ 0 },
};
@ -734,91 +796,92 @@ static struct ti_dt_clk dra7xx_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"),
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"),
DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),
{ .node_name = NULL },
};
@ -827,7 +890,10 @@ int __init dra7xx_dt_clk_init(void)
int rc;
struct clk *dpll_ck, *hdcp_ck;
ti_dt_clocks_register(dra7xx_clks);
if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
ti_dt_clocks_register(dra7xx_compat_clks);
else
ti_dt_clocks_register(dra7xx_clks);
omap2_clk_disable_autoidle_all();

18
drivers/clk/ti/clk.c
View File

@ -34,7 +34,7 @@
struct ti_clk_ll_ops *ti_clk_ll_ops;
static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS];
static struct ti_clk_features ti_clk_features;
struct ti_clk_features ti_clk_features;
struct clk_iomap {
struct regmap *regmap;
@ -129,7 +129,7 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
{
struct ti_dt_clk *c;
struct device_node *node;
struct device_node *node, *parent;
struct clk *clk;
struct of_phandle_args clkspec;
char buf[64];
@ -140,6 +140,9 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
int ret;
static bool clkctrl_nodes_missing;
static bool has_clkctrl_data;
static bool compat_mode;
compat_mode = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT;
for (c = oclks; c->node_name != NULL; c++) {
strcpy(buf, c->node_name);
@ -164,8 +167,12 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
continue;
node = of_find_node_by_name(NULL, buf);
if (num_args)
node = of_find_node_by_name(node, "clk");
if (num_args && compat_mode) {
parent = node;
node = of_get_child_by_name(parent, "clk");
of_node_put(parent);
}
clkspec.np = node;
clkspec.args_count = num_args;
for (i = 0; i < num_args; i++) {
@ -173,11 +180,12 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
if (ret) {
pr_warn("Bad tag in %s at %d: %s\n",
c->node_name, i, tags[i]);
of_node_put(node);
return;
}
}
clk = of_clk_get_from_provider(&clkspec);
of_node_put(node);
if (!IS_ERR(clk)) {
c->lk.clk = clk;
clkdev_add(&c->lk);

104
drivers/clk/ti/clkctrl.c
View File

@ -259,8 +259,13 @@ _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
struct omap_clkctrl_clk *clkctrl_clk;
int ret = 0;
init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d", node->parent->name,
node->name, offset, bit);
if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d",
node->parent->name, node->name, offset,
bit);
else
init.name = kasprintf(GFP_KERNEL, "%s:%04x:%d", node->name,
offset, bit);
clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
if (!init.name || !clkctrl_clk) {
ret = -ENOMEM;
@ -440,6 +445,11 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
const __be32 *addrp;
u32 addr;
int ret;
char *c;
if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
!strcmp(node->name, "clk"))
ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT;
addrp = of_get_address(node, 0, NULL, NULL);
addr = (u32)of_translate_address(node, addrp);
@ -453,18 +463,35 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
data = omap5_clkctrl_data;
#endif
#ifdef CONFIG_SOC_DRA7XX
if (of_machine_is_compatible("ti,dra7"))
data = dra7_clkctrl_data;
if (of_machine_is_compatible("ti,dra7")) {
if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
data = dra7_clkctrl_compat_data;
else
data = dra7_clkctrl_data;
}
#endif
#ifdef CONFIG_SOC_AM33XX
if (of_machine_is_compatible("ti,am33xx"))
data = am3_clkctrl_data;
if (of_machine_is_compatible("ti,am33xx")) {
if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
data = am3_clkctrl_compat_data;
else
data = am3_clkctrl_data;
}
#endif
#ifdef CONFIG_SOC_AM43XX
if (of_machine_is_compatible("ti,am4372"))
data = am4_clkctrl_data;
if (of_machine_is_compatible("ti,am438x"))
data = am438x_clkctrl_data;
if (of_machine_is_compatible("ti,am4372")) {
if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
data = am4_clkctrl_compat_data;
else
data = am4_clkctrl_data;
}
if (of_machine_is_compatible("ti,am438x")) {
if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
data = am438x_clkctrl_compat_data;
else
data = am438x_clkctrl_data;
}
#endif
#ifdef CONFIG_SOC_TI81XX
if (of_machine_is_compatible("ti,dm814"))
@ -492,21 +519,46 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
provider->base = of_iomap(node, 0);
provider->clkdm_name = kmalloc(strlen(node->parent->name) + 3,
GFP_KERNEL);
if (!provider->clkdm_name) {
kfree(provider);
return;
if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) {
provider->clkdm_name = kmalloc(strlen(node->parent->name) + 3,
GFP_KERNEL);
if (!provider->clkdm_name) {
kfree(provider);
return;
}
/*
* Create default clkdm name, replace _cm from end of parent
* node name with _clkdm
*/
strcpy(provider->clkdm_name, node->parent->name);
provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
} else {
provider->clkdm_name = kmalloc(strlen(node->name), GFP_KERNEL);
if (!provider->clkdm_name) {
kfree(provider);
return;
}
/*
* Create default clkdm name, replace _clkctrl from end of
* node name with _clkdm
*/
strcpy(provider->clkdm_name, node->name);
provider->clkdm_name[strlen(provider->clkdm_name) - 7] = 0;
}
/*
* Create default clkdm name, replace _cm from end of parent node
* name with _clkdm
*/
strcpy(provider->clkdm_name, node->parent->name);
provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
strcat(provider->clkdm_name, "clkdm");
/* Replace any dash from the clkdm name with underscore */
c = provider->clkdm_name;
while (*c) {
if (*c == '-')
*c = '_';
c++;
}
INIT_LIST_HEAD(&provider->clocks);
/* Generate clocks */
@ -539,9 +591,13 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
init.flags = 0;
if (reg_data->flags & CLKF_SET_RATE_PARENT)
init.flags |= CLK_SET_RATE_PARENT;
init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d",
node->parent->name, node->name,
reg_data->offset, 0);
if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d",
node->parent->name, node->name,
reg_data->offset, 0);
else
init.name = kasprintf(GFP_KERNEL, "%s:%04x:%d",
node->name, reg_data->offset, 0);
clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
if (!init.name || !clkctrl_clk)
goto cleanup;

11
drivers/clk/ti/clock.h
View File

@ -24,6 +24,7 @@ struct clk_omap_divider {
u8 flags;
s8 latch;
const struct clk_div_table *table;
u32 context;
};
#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
@ -36,6 +37,7 @@ struct clk_omap_mux {
u8 shift;
s8 latch;
u8 flags;
u8 saved_parent;
};
#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
@ -184,9 +186,16 @@ struct omap_clkctrl_data {
extern const struct omap_clkctrl_data omap4_clkctrl_data[];
extern const struct omap_clkctrl_data omap5_clkctrl_data[];
extern const struct omap_clkctrl_data dra7_clkctrl_data[];
extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[];
extern struct ti_dt_clk dra7xx_compat_clks[];
extern const struct omap_clkctrl_data am3_clkctrl_data[];
extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
extern struct ti_dt_clk am33xx_compat_clks[];
extern const struct omap_clkctrl_data am4_clkctrl_data[];
extern const struct omap_clkctrl_data am4_clkctrl_compat_data[];
extern struct ti_dt_clk am43xx_compat_clks[];
extern const struct omap_clkctrl_data am438x_clkctrl_data[];
extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[];
extern const struct omap_clkctrl_data dm814_clkctrl_data[];
extern const struct omap_clkctrl_data dm816_clkctrl_data[];
@ -233,6 +242,8 @@ extern const struct clk_ops ti_clk_divider_ops;
extern const struct clk_ops ti_clk_mux_ops;
extern const struct clk_ops omap_gate_clk_ops;
extern struct ti_clk_features ti_clk_features;
void omap2_init_clk_clkdm(struct clk_hw *hw);
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);

36
drivers/clk/ti/divider.c
View File

@ -268,10 +268,46 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
/**
* clk_divider_save_context - Save the divider value
* @hw: pointer struct clk_hw
*
* Save the divider value
*/
static int clk_divider_save_context(struct clk_hw *hw)
{
struct clk_omap_divider *divider = to_clk_omap_divider(hw);
u32 val;
val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
divider->context = val & div_mask(divider);
return 0;
}
/**
* clk_divider_restore_context - restore the saved the divider value
* @hw: pointer struct clk_hw
*
* Restore the saved the divider value
*/
static void clk_divider_restore_context(struct clk_hw *hw)
{
struct clk_omap_divider *divider = to_clk_omap_divider(hw);
u32 val;
val = ti_clk_ll_ops->clk_readl(&divider->reg);
val &= ~(div_mask(divider) << divider->shift);
val |= divider->context << divider->shift;
ti_clk_ll_ops->clk_writel(val, &divider->reg);
}
const struct clk_ops ti_clk_divider_ops = {
.recalc_rate = ti_clk_divider_recalc_rate,
.round_rate = ti_clk_divider_round_rate,
.set_rate = ti_clk_divider_set_rate,
.save_context = clk_divider_save_context,
.restore_context = clk_divider_restore_context,
};
static struct clk *_register_divider(struct device *dev, const char *name,

6
drivers/clk/ti/dpll.c
View File

@ -39,6 +39,8 @@ static const struct clk_ops dpll_m4xen_ck_ops = {
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
.determine_rate = &omap4_dpll_regm4xen_determine_rate,
.get_parent = &omap2_init_dpll_parent,
.save_context = &omap3_core_dpll_save_context,
.restore_context = &omap3_core_dpll_restore_context,
};
#else
static const struct clk_ops dpll_m4xen_ck_ops = {};
@ -62,6 +64,8 @@ static const struct clk_ops dpll_ck_ops = {
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
.determine_rate = &omap3_noncore_dpll_determine_rate,
.get_parent = &omap2_init_dpll_parent,
.save_context = &omap3_noncore_dpll_save_context,
.restore_context = &omap3_noncore_dpll_restore_context,
};
static const struct clk_ops dpll_no_gate_ck_ops = {
@ -72,6 +76,8 @@ static const struct clk_ops dpll_no_gate_ck_ops = {
.set_parent = &omap3_noncore_dpll_set_parent,
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
.determine_rate = &omap3_noncore_dpll_determine_rate,
.save_context = &omap3_noncore_dpll_save_context,
.restore_context = &omap3_noncore_dpll_restore_context
};
#else
static const struct clk_ops dpll_core_ck_ops = {};

124
drivers/clk/ti/dpll3xxx.c
View File

@ -782,6 +782,130 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
return rate;
}
/**
* omap3_core_dpll_save_context - Save the m and n values of the divider
* @hw: pointer struct clk_hw
*
* Before the dpll registers are lost save the last rounded rate m and n
* and the enable mask.
*/
int omap3_core_dpll_save_context(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *dd;
u32 v;
dd = clk->dpll_data;
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
if (clk->context == DPLL_LOCKED) {
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
dd->last_rounded_m = (v & dd->mult_mask) >>
__ffs(dd->mult_mask);
dd->last_rounded_n = ((v & dd->div1_mask) >>
__ffs(dd->div1_mask)) + 1;
}
return 0;
}
/**
* omap3_core_dpll_restore_context - restore the m and n values of the divider
* @hw: pointer struct clk_hw
*
* Restore the last rounded rate m and n
* and the enable mask.
*/
void omap3_core_dpll_restore_context(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
const struct dpll_data *dd;
u32 v;
dd = clk->dpll_data;
if (clk->context == DPLL_LOCKED) {
_omap3_dpll_write_clken(clk, 0x4);
_omap3_wait_dpll_status(clk, 0);
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
v &= ~(dd->mult_mask | dd->div1_mask);
v |= dd->last_rounded_m << __ffs(dd->mult_mask);
v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
_omap3_dpll_write_clken(clk, DPLL_LOCKED);
_omap3_wait_dpll_status(clk, 1);
} else {
_omap3_dpll_write_clken(clk, clk->context);
}
}
/**
* omap3_non_core_dpll_save_context - Save the m and n values of the divider
* @hw: pointer struct clk_hw
*
* Before the dpll registers are lost save the last rounded rate m and n
* and the enable mask.
*/
int omap3_noncore_dpll_save_context(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *dd;
u32 v;
dd = clk->dpll_data;
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
if (clk->context == DPLL_LOCKED) {
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
dd->last_rounded_m = (v & dd->mult_mask) >>
__ffs(dd->mult_mask);
dd->last_rounded_n = ((v & dd->div1_mask) >>
__ffs(dd->div1_mask)) + 1;
}
return 0;
}
/**
* omap3_core_dpll_restore_context - restore the m and n values of the divider
* @hw: pointer struct clk_hw
*
* Restore the last rounded rate m and n
* and the enable mask.
*/
void omap3_noncore_dpll_restore_context(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
const struct dpll_data *dd;
u32 ctrl, mult_div1;
dd = clk->dpll_data;
ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
if (clk->context == ((ctrl & dd->enable_mask) >>
__ffs(dd->enable_mask)) &&
dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >>
__ffs(dd->mult_mask)) &&
dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >>
__ffs(dd->div1_mask)) + 1) {
/* nothing to be done */
return;
}
if (clk->context == DPLL_LOCKED)
omap3_noncore_dpll_program(clk, 0);
else
_omap3_dpll_write_clken(clk, clk->context);
}
/* OMAP3/4 non-CORE DPLL clkops */
const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
.allow_idle = omap3_dpll_allow_idle,

3
drivers/clk/ti/gate.c
View File

@ -33,6 +33,7 @@ static const struct clk_ops omap_gate_clkdm_clk_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap2_clkops_enable_clkdm,
.disable = &omap2_clkops_disable_clkdm,
.restore_context = clk_gate_restore_context,
};
const struct clk_ops omap_gate_clk_ops = {
@ -40,6 +41,7 @@ const struct clk_ops omap_gate_clk_ops = {
.enable = &omap2_dflt_clk_enable,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
.restore_context = clk_gate_restore_context,
};
static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
@ -47,6 +49,7 @@ static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
.enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
.restore_context = clk_gate_restore_context,
};
/**

29
drivers/clk/ti/mux.c
View File

@ -91,10 +91,39 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
return 0;
}
/**
* clk_mux_save_context - Save the parent selcted in the mux
* @hw: pointer struct clk_hw
*
* Save the parent mux value.
*/
static int clk_mux_save_context(struct clk_hw *hw)
{
struct clk_omap_mux *mux = to_clk_omap_mux(hw);
mux->saved_parent = ti_clk_mux_get_parent(hw);
return 0;
}
/**
* clk_mux_restore_context - Restore the parent in the mux
* @hw: pointer struct clk_hw
*
* Restore the saved parent mux value.
*/
static void clk_mux_restore_context(struct clk_hw *hw)
{
struct clk_omap_mux *mux = to_clk_omap_mux(hw);
ti_clk_mux_set_parent(hw, mux->saved_parent);
}
const struct clk_ops ti_clk_mux_ops = {
.get_parent = ti_clk_mux_get_parent,
.set_parent = ti_clk_mux_set_parent,
.determine_rate = __clk_mux_determine_rate,
.save_context = clk_mux_save_context,
.restore_context = clk_mux_restore_context,
};
static struct clk *_register_mux(struct device *dev, const char *name,

119
include/dt-bindings/clock/am3.h
View File

@ -16,6 +16,8 @@
#define AM3_CLKCTRL_OFFSET 0x0
#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* l4_per clocks */
#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
@ -105,4 +107,121 @@
#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
/* XXX: Compatibility part end */
/* l4ls clocks */
#define AM3_L4LS_CLKCTRL_OFFSET 0x38
#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)
#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38)
#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c)
#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40)
#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44)
#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48)
#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c)
#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50)
#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60)
#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c)
#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70)
#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74)
#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78)
#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c)
#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80)
#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84)
#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88)
#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90)
#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac)
#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0)
#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4)
#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0)
#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4)
#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc)
#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4)
#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8)
#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec)
#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0)
#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4)
#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c)
#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110)
#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130)
/* l3s clocks */
#define AM3_L3S_CLKCTRL_OFFSET 0x1c
#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET)
#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c)
#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30)
#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34)
#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68)
#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8)
/* l3 clocks */
#define AM3_L3_CLKCTRL_OFFSET 0x24
#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET)
#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24)
#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28)
#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c)
#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94)
#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0)
#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc)
#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc)
#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0)
#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc)
#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100)
/* l4hs clocks */
#define AM3_L4HS_CLKCTRL_OFFSET 0x120
#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET)
#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120)
/* pruss_ocp clocks */
#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8
#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
/* cpsw_125mhz clocks */
#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14)
/* lcdc clocks */
#define AM3_LCDC_CLKCTRL_OFFSET 0x18
#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET)
#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18)
/* clk_24mhz clocks */
#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c
#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
/* l4_wkup clocks */
#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8)
#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc)
#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4)
#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8)
#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc)
#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0)
#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4)
#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8)
#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4)
/* l3_aon clocks */
#define AM3_L3_AON_CLKCTRL_OFFSET 0x14
#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14)
/* l4_wkup_aon clocks */
#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0
#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
/* mpu clocks */
#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
/* l4_rtc clocks */
#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
/* gfx_l3 clocks */
#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
/* l4_cefuse clocks */
#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20)
#endif

132
include/dt-bindings/clock/am4.h
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@ -16,6 +16,8 @@
#define AM4_CLKCTRL_OFFSET 0x20
#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* l4_wkup clocks */
#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
@ -110,4 +112,134 @@
#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
/* XXX: Compatibility part end. */
/* l3s_tsc clocks */
#define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
#define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET)
#define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
/* l4_wkup_aon clocks */
#define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
#define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET)
#define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
#define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
/* l4_wkup clocks */
#define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
#define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET)
#define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
#define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
#define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
#define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340)
#define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348)
#define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350)
#define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358)
#define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360)
#define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368)
/* mpu clocks */
#define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* gfx_l3 clocks */
#define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* l4_rtc clocks */
#define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* l3 clocks */
#define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
#define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
#define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
#define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
#define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
#define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
#define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
#define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
#define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
#define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
#define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
/* l3s clocks */
#define AM4_L3S_CLKCTRL_OFFSET 0x68
#define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET)
#define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68)
#define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70)
#define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220)
#define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238)
#define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240)
#define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248)
#define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258)
#define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260)
#define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268)
/* pruss_ocp clocks */
#define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320
#define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET)
#define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320)
/* l4ls clocks */
#define AM4_L4LS_CLKCTRL_OFFSET 0x420
#define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET)
#define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420)
#define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428)
#define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430)
#define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438)
#define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440)
#define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448)
#define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450)
#define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458)
#define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460)
#define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468)
#define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478)
#define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480)
#define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488)
#define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490)
#define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498)
#define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0)
#define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8)
#define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0)
#define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8)
#define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0)
#define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8)
#define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0)
#define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500)
#define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508)
#define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510)
#define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518)
#define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520)
#define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528)
#define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530)
#define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538)
#define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540)
#define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548)
#define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550)
#define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558)
#define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560)
#define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568)
#define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570)
#define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578)
#define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580)
#define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588)
#define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590)
#define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598)
#define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0)
#define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8)
#define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0)
/* emif clocks */
#define AM4_EMIF_CLKCTRL_OFFSET 0x720
#define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET)
#define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720)
/* dss clocks */
#define AM4_DSS_CLKCTRL_OFFSET 0xa20
#define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET)
#define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20)
/* cpsw_125mhz clocks */
#define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20
#define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET)
#define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20)
#endif

326
include/dt-bindings/clock/dra7.h
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@ -16,19 +16,21 @@
#define DRA7_CLKCTRL_OFFSET 0x20
#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* mpu clocks */
#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* ipu clocks */
#define DRA7_IPU_CLKCTRL_OFFSET 0x40
#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
#define _DRA7_IPU_CLKCTRL_OFFSET 0x40
#define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET)
#define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50)
#define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58)
#define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60)
#define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68)
#define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70)
#define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78)
#define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80)
/* rtc clocks */
#define DRA7_RTC_CLKCTRL_OFFSET 0x40
@ -99,65 +101,65 @@
#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
/* l4per clocks */
#define DRA7_L4PER_CLKCTRL_OFFSET 0x0
#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc)
#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14)
#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90)
#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98)
#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4)
#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8)
#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0)
#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8)
#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130)
#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138)
#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160)
#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168)
#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178)
#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190)
#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198)
#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204)
#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208)
#define _DRA7_L4PER_CLKCTRL_OFFSET 0x0
#define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET)
#define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc)
#define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14)
#define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28)
#define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30)
#define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38)
#define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40)
#define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48)
#define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50)
#define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58)
#define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60)
#define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68)
#define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70)
#define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78)
#define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80)
#define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88)
#define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90)
#define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98)
#define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0)
#define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8)
#define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0)
#define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8)
#define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0)
#define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4)
#define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8)
#define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0)
#define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8)
#define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0)
#define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8)
#define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100)
#define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108)
#define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110)
#define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118)
#define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120)
#define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128)
#define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130)
#define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138)
#define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140)
#define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148)
#define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150)
#define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158)
#define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160)
#define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168)
#define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170)
#define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178)
#define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190)
#define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198)
#define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
#define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
#define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
#define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
#define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
#define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
#define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
#define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
#define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
#define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204)
#define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208)
/* wkupaon clocks */
#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
@ -170,4 +172,192 @@
#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
/* XXX: Compatibility part end. */
/* mpu clocks */
#define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* dsp1 clocks */
#define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* ipu1 clocks */
#define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* ipu clocks */
#define DRA7_IPU_CLKCTRL_OFFSET 0x50
#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
#define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
#define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
#define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
#define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
#define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
#define DRA7_IPU_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
#define DRA7_IPU_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
/* dsp2 clocks */
#define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* rtc clocks */
#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44)
/* coreaon clocks */
#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
/* l3main1 clocks */
#define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
#define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
#define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
/* ipu2 clocks */
#define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* dma clocks */
#define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* emif clocks */
#define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* atl clocks */
#define DRA7_ATL_CLKCTRL_OFFSET 0x0
#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
#define DRA7_ATL_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)
/* l4cfg clocks */
#define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
#define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
#define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
#define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
#define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
#define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
#define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
#define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
/* l3instr clocks */
#define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* dss clocks */
#define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* l3init clocks */
#define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
#define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
#define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
#define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
/* pcie clocks */
#define DRA7_PCIE_CLKCTRL_OFFSET 0xb0
#define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET)
#define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0)
#define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8)
/* gmac clocks */
#define DRA7_GMAC_CLKCTRL_OFFSET 0xd0
#define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET)
#define DRA7_GMAC_GMAC_CLKCTRL DRA7_GMAC_CLKCTRL_INDEX(0xd0)
/* l4per clocks */
#define DRA7_L4PER_CLKCTRL_OFFSET 0x28
#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
#define DRA7_L4PER_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
#define DRA7_L4PER_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
#define DRA7_L4PER_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
#define DRA7_L4PER_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
#define DRA7_L4PER_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
#define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
#define DRA7_L4PER_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
#define DRA7_L4PER_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
#define DRA7_L4PER_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
#define DRA7_L4PER_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
#define DRA7_L4PER_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
#define DRA7_L4PER_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
#define DRA7_L4PER_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
#define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
#define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
#define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
#define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
#define DRA7_L4PER_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
#define DRA7_L4PER_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
#define DRA7_L4PER_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
#define DRA7_L4PER_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
#define DRA7_L4PER_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
#define DRA7_L4PER_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
#define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
#define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
#define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
#define DRA7_L4PER_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
#define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
#define DRA7_L4PER_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
#define DRA7_L4PER_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
#define DRA7_L4PER_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
/* l4sec clocks */
#define DRA7_L4SEC_CLKCTRL_OFFSET 0x1a0
#define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET)
#define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0)
#define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8)
#define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
#define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
#define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
/* l4per2 clocks */
#define DRA7_L4PER2_CLKCTRL_OFFSET 0xc
#define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET)
#define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc)
#define DRA7_L4PER2_PRUSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x18)
#define DRA7_L4PER2_PRUSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x20)
#define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90)
#define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98)
#define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4)
#define DRA7_L4PER2_QSPI_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x138)
#define DRA7_L4PER2_MCASP2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x160)
#define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168)
#define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178)
#define DRA7_L4PER2_MCASP8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x190)
#define DRA7_L4PER2_MCASP4_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x198)
#define DRA7_L4PER2_UART7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1d0)
#define DRA7_L4PER2_UART8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e0)
#define DRA7_L4PER2_UART9_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e8)
#define DRA7_L4PER2_DCAN2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1f0)
#define DRA7_L4PER2_MCASP6_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x204)
#define DRA7_L4PER2_MCASP7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x208)
/* l4per3 clocks */
#define DRA7_L4PER3_CLKCTRL_OFFSET 0x14
#define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET)
#define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14)
#define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8)
#define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0)
#define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8)
#define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130)
/* wkupaon clocks */
#define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
#define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
#define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
#endif

9
include/linux/clk-provider.h
View File

@ -119,6 +119,11 @@ struct clk_duty {
* Called with enable_lock held. This function must not
* sleep.
*
* @save_context: Save the context of the clock in prepration for poweroff.
*
* @restore_context: Restore the context of the clock after a restoration
* of power.
*
* @recalc_rate Recalculate the rate of this clock, by querying hardware. The
* parent rate is an input parameter. It is up to the caller to
* ensure that the prepare_mutex is held across this call.
@ -223,6 +228,8 @@ struct clk_ops {
void (*disable)(struct clk_hw *hw);
int (*is_enabled)(struct clk_hw *hw);
void (*disable_unused)(struct clk_hw *hw);
int (*save_context)(struct clk_hw *hw);
void (*restore_context)(struct clk_hw *hw);
unsigned long (*recalc_rate)(struct clk_hw *hw,
unsigned long parent_rate);
long (*round_rate)(struct clk_hw *hw, unsigned long rate,
@ -1011,5 +1018,7 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
#endif /* platform dependent I/O accessors */
void clk_gate_restore_context(struct clk_hw *hw);
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */

25
include/linux/clk.h
View File

@ -629,6 +629,23 @@ struct clk *clk_get_parent(struct clk *clk);
*/
struct clk *clk_get_sys(const char *dev_id, const char *con_id);
/**
* clk_save_context - save clock context for poweroff
*
* Saves the context of the clock register for powerstates in which the
* contents of the registers will be lost. Occurs deep within the suspend
* code so locking is not necessary.
*/
int clk_save_context(void);
/**
* clk_restore_context - restore clock context after poweroff
*
* This occurs with all clocks enabled. Occurs deep within the resume code
* so locking is not necessary.
*/
void clk_restore_context(void);
#else /* !CONFIG_HAVE_CLK */
static inline struct clk *clk_get(struct device *dev, const char *id)
@ -728,6 +745,14 @@ static inline struct clk *clk_get_sys(const char *dev_id, const char *con_id)
{
return NULL;
}
static inline int clk_save_context(void)
{
return 0;
}
static inline void clk_restore_context(void) {}
#endif
/* clk_prepare_enable helps cases using clk_enable in non-atomic context. */

7
include/linux/clk/ti.h
View File

@ -159,6 +159,7 @@ struct clk_hw_omap {
const char *clkdm_name;
struct clockdomain *clkdm;
const struct clk_hw_omap_ops *ops;
u32 context;
};
/*
@ -290,9 +291,15 @@ struct ti_clk_features {
#define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1)
#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2)
#define TI_CLK_ERRATA_I810 BIT(3)
#define TI_CLK_CLKCTRL_COMPAT BIT(4)
void ti_clk_setup_features(struct ti_clk_features *features);
const struct ti_clk_features *ti_clk_get_features(void);
int omap3_noncore_dpll_save_context(struct clk_hw *hw);
void omap3_noncore_dpll_restore_context(struct clk_hw *hw);
int omap3_core_dpll_save_context(struct clk_hw *hw);
void omap3_core_dpll_restore_context(struct clk_hw *hw);
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;