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ARM: dts: mediatek: Enable clock support for Mediatek MT8135.
This patch adds MT8135 clock controllers into device tree. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -12,6 +12,7 @@
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/mt8135-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton64.dtsi"
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@ -94,6 +95,11 @@ uart_clk: dummy26m {
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#clock-cells = <0>;
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};
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clk26m: clk26m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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};
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soc {
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@ -102,6 +108,26 @@ soc {
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compatible = "simple-bus";
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ranges;
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topckgen: topckgen@10000000 {
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compatible = "mediatek,mt8135-topckgen";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: infracfg@10001000 {
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#reset-cells = <1>;
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#clock-cells = <1>;
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compatible = "mediatek,mt8135-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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};
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pericfg: pericfg@10003000 {
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#reset-cells = <1>;
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#clock-cells = <1>;
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compatible = "mediatek,mt8135-pericfg", "syscon";
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reg = <0 0x10003000 0 0x1000>;
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};
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/*
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* Pinctrl access register at 0x10005000 and 0x1020c000 through
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* regmap. Register 0x1000b000 is used by EINT.
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@ -143,6 +169,12 @@ sysirq: interrupt-controller@10200030 {
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reg = <0 0x10200030 0 0x1c>;
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};
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apmixedsys: apmixedsys@10209000 {
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compatible = "mediatek,mt8135-apmixedsys";
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reg = <0 0x10209000 0 0x1000>;
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#clock-cells = <1>;
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};
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syscfg_pctl_b: syscfg_pctl_b@1020c000 {
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compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
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reg = <0 0x1020c000 0 0x1000>;
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