ARM: dts: mediatek: Enable clock support for Mediatek MT8135.

This patch adds MT8135 clock controllers into device tree.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
James Liao 2015-07-07 14:45:10 +02:00 committed by Matthias Brugger
parent d770e558e2
commit 3cc17a5c26

View File

@ -12,6 +12,7 @@
* GNU General Public License for more details.
*/
#include <dt-bindings/clock/mt8135-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton64.dtsi"
@ -94,6 +95,11 @@ uart_clk: dummy26m {
#clock-cells = <0>;
};
clk26m: clk26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
};
soc {
@ -102,6 +108,26 @@ soc {
compatible = "simple-bus";
ranges;
topckgen: topckgen@10000000 {
compatible = "mediatek,mt8135-topckgen";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg: infracfg@10001000 {
#reset-cells = <1>;
#clock-cells = <1>;
compatible = "mediatek,mt8135-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
};
pericfg: pericfg@10003000 {
#reset-cells = <1>;
#clock-cells = <1>;
compatible = "mediatek,mt8135-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
};
/*
* Pinctrl access register at 0x10005000 and 0x1020c000 through
* regmap. Register 0x1000b000 is used by EINT.
@ -143,6 +169,12 @@ sysirq: interrupt-controller@10200030 {
reg = <0 0x10200030 0 0x1c>;
};
apmixedsys: apmixedsys@10209000 {
compatible = "mediatek,mt8135-apmixedsys";
reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>;
};
syscfg_pctl_b: syscfg_pctl_b@1020c000 {
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
reg = <0 0x1020c000 0 0x1000>;