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drm/i915: Power Context register is only available for gen4 mobiles

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The ability to save the hardware context upon powering down the render
clock through PWRCTXA is only available on a couple of gen4 chipsets.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2010-12-05 16:45:02 +00:00
parent 88f23b8fa3
commit 3c8cdf9b60
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/intel_display.c
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@ -5973,7 +5973,7 @@ void intel_init_clock_gating(struct drm_device *dev)
"Disable RC6\n");
}
if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
if (IS_GEN4(dev) && IS_MOBILE(dev)) {
if (dev_priv->pwrctx == NULL)
dev_priv->pwrctx = intel_alloc_context_page(dev);
if (dev_priv->pwrctx) {