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clk: exynos4: Fix incorrect placement of __initdata
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -194,7 +194,7 @@ enum exynos4_clks {
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* list of controller registers to be saved and restored during a
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* list of controller registers to be saved and restored during a
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* suspend/resume cycle.
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* suspend/resume cycle.
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*/
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*/
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static __initdata unsigned long exynos4210_clk_save[] = {
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static unsigned long exynos4210_clk_save[] __initdata = {
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E4210_SRC_IMAGE,
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E4210_SRC_IMAGE,
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E4210_SRC_LCD1,
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E4210_SRC_LCD1,
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E4210_SRC_MASK_LCD1,
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E4210_SRC_MASK_LCD1,
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@ -205,7 +205,7 @@ static __initdata unsigned long exynos4210_clk_save[] = {
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E4210_MPLL_CON0,
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E4210_MPLL_CON0,
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};
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};
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static __initdata unsigned long exynos4x12_clk_save[] = {
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static unsigned long exynos4x12_clk_save[] __initdata = {
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E4X12_GATE_IP_IMAGE,
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E4X12_GATE_IP_IMAGE,
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E4X12_GATE_IP_PERIR,
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E4X12_GATE_IP_PERIR,
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E4X12_SRC_CAM1,
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E4X12_SRC_CAM1,
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@ -214,7 +214,7 @@ static __initdata unsigned long exynos4x12_clk_save[] = {
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E4X12_MPLL_CON0,
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E4X12_MPLL_CON0,
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};
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};
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static __initdata unsigned long exynos4_clk_regs[] = {
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static unsigned long exynos4_clk_regs[] __initdata = {
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SRC_LEFTBUS,
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SRC_LEFTBUS,
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DIV_LEFTBUS,
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DIV_LEFTBUS,
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GATE_IP_LEFTBUS,
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GATE_IP_LEFTBUS,
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@ -978,13 +978,13 @@ static void __init exynos4_clk_register_finpll(unsigned long xom)
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}
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}
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static __initdata struct of_device_id ext_clk_match[] = {
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static struct of_device_id ext_clk_match[] __initdata = {
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{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
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{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
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{ .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
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{ .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
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{},
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{},
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};
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};
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static struct __initdata samsung_pll_clock exynos4_plls[nr_plls] = {
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static struct samsung_pll_clock exynos4_plls[nr_plls] __initdata = {
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[apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
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[apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
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APLL_CON0, "fout_apll", NULL),
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APLL_CON0, "fout_apll", NULL),
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[mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll",
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[mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll",
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