AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-28 11:18:45 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

drm/i915: BDW needs D_COMP writes through MCHBAR

Browse Source 
That's what the spec said! And HSW needs it through pcode (you can
only read it through MCHBAR), so create hsw_write_dcomp to abstract
the weirdness.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Paulo Zanoni 2014-03-07 20:12:36 -03:00 committed by Daniel Vetter
parent 414de7a020
commit 3c4c9b819f
1 changed files with 18 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
drivers/gpu/drm/i915/intel_display.c
View File

@ -6885,6 +6885,22 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
} }
static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
{
struct drm_device *dev = dev_priv->dev;
if (IS_HASWELL(dev)) {
mutex_lock(&dev_priv->rps.hw_lock);
if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
val))
DRM_ERROR("Failed to disable D_COMP\n");
mutex_unlock(&dev_priv->rps.hw_lock);
} else {
I915_WRITE(D_COMP, val);
}
POSTING_READ(D_COMP);
}
/* /*
* This function implements pieces of two sequences from BSpec: * This function implements pieces of two sequences from BSpec:
* - Sequence for display software to disable LCPLL * - Sequence for display software to disable LCPLL
@ -6922,11 +6938,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
val = I915_READ(D_COMP); val = I915_READ(D_COMP);
val |= D_COMP_COMP_DISABLE; val |= D_COMP_COMP_DISABLE;
mutex_lock(&dev_priv->rps.hw_lock); hsw_write_dcomp(dev_priv, val);
if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
DRM_ERROR("Failed to disable D_COMP\n");
mutex_unlock(&dev_priv->rps.hw_lock);
POSTING_READ(D_COMP);
ndelay(100); ndelay(100);
if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
@ -6981,11 +6993,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
val = I915_READ(D_COMP); val = I915_READ(D_COMP);
val |= D_COMP_COMP_FORCE; val |= D_COMP_COMP_FORCE;
val &= ~D_COMP_COMP_DISABLE; val &= ~D_COMP_COMP_DISABLE;
mutex_lock(&dev_priv->rps.hw_lock); hsw_write_dcomp(dev_priv, val);
if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
DRM_ERROR("Failed to enable D_COMP\n");
mutex_unlock(&dev_priv->rps.hw_lock);
POSTING_READ(D_COMP);
val = I915_READ(LCPLL_CTL); val = I915_READ(LCPLL_CTL);
val &= ~LCPLL_PLL_DISABLE; val &= ~LCPLL_PLL_DISABLE;