AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-26 11:00:53 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

qla4xxx: Added PEX DMA Support for ISP8022 Adapter

Browse Source 
Signed-off-by: Tej Parkash <tej.parkash@qlogic.com>
Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com>
Reviewed-by: Mike Christie <michaelc@cs.wisc.edu>
Signed-off-by: Christoph Hellwig <hch@lst.de>
This commit is contained in:
Tej Parkash 2014-02-24 22:07:00 -05:00 committed by Christoph Hellwig
parent b182978945
commit 3c3cab1727
3 changed files with 28 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
drivers/scsi/qla4xxx/ql4_83xx.c
View File

@ -250,7 +250,7 @@ void qla4_83xx_rom_lock_recovery(struct scsi_qla_host *ha)
} }
/** /**
* qla4_83xx_ms_mem_write_128b - Writes data to MS/off-chip memory * qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory
* @ha: Pointer to adapter structure * @ha: Pointer to adapter structure
* @addr: Flash address to write to * @addr: Flash address to write to
* @data: Data to be written * @data: Data to be written
@ -259,7 +259,7 @@ void qla4_83xx_rom_lock_recovery(struct scsi_qla_host *ha)
* Return: On success return QLA_SUCCESS * Return: On success return QLA_SUCCESS
* On error return QLA_ERROR * On error return QLA_ERROR
**/ **/
int qla4_83xx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr, int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
uint32_t *data, uint32_t count) uint32_t *data, uint32_t count)
{ {
int i, j; int i, j;
@ -276,7 +276,7 @@ int qla4_83xx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
write_lock_irqsave(&ha->hw_lock, flags); write_lock_irqsave(&ha->hw_lock, flags);
/* Write address */ /* Write address */
ret_val = qla4_83xx_wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0); ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0);
if (ret_val == QLA_ERROR) { if (ret_val == QLA_ERROR) {
ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n", ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n",
__func__); __func__);
@ -292,19 +292,20 @@ int qla4_83xx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
goto exit_ms_mem_write_unlock; goto exit_ms_mem_write_unlock;
} }
ret_val = qla4_83xx_wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO, ret_val = ha->isp_ops->wr_reg_indirect(ha,
addr); MD_MIU_TEST_AGT_ADDR_LO,
addr);
/* Write data */ /* Write data */
ret_val |= qla4_83xx_wr_reg_indirect(ha, ret_val |= ha->isp_ops->wr_reg_indirect(ha,
MD_MIU_TEST_AGT_WRDATA_LO, MD_MIU_TEST_AGT_WRDATA_LO,
*data++); *data++);
ret_val |= qla4_83xx_wr_reg_indirect(ha, ret_val |= ha->isp_ops->wr_reg_indirect(ha,
MD_MIU_TEST_AGT_WRDATA_HI, MD_MIU_TEST_AGT_WRDATA_HI,
*data++); *data++);
ret_val |= qla4_83xx_wr_reg_indirect(ha, ret_val |= ha->isp_ops->wr_reg_indirect(ha,
MD_MIU_TEST_AGT_WRDATA_ULO, MD_MIU_TEST_AGT_WRDATA_ULO,
*data++); *data++);
ret_val |= qla4_83xx_wr_reg_indirect(ha, ret_val |= ha->isp_ops->wr_reg_indirect(ha,
MD_MIU_TEST_AGT_WRDATA_UHI, MD_MIU_TEST_AGT_WRDATA_UHI,
*data++); *data++);
if (ret_val == QLA_ERROR) { if (ret_val == QLA_ERROR) {
@ -314,10 +315,11 @@ int qla4_83xx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
} }
/* Check write status */ /* Check write status */
ret_val = qla4_83xx_wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
MIU_TA_CTL_WRITE_ENABLE); MIU_TA_CTL_WRITE_ENABLE);
ret_val |= qla4_83xx_wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, ret_val |= ha->isp_ops->wr_reg_indirect(ha,
MIU_TA_CTL_WRITE_START); MD_MIU_TEST_AGT_CTRL,
MIU_TA_CTL_WRITE_START);
if (ret_val == QLA_ERROR) { if (ret_val == QLA_ERROR) {
ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n", ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n",
__func__); __func__);
@ -325,9 +327,9 @@ int qla4_83xx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
} }
for (j = 0; j < MAX_CTL_CHECK; j++) { for (j = 0; j < MAX_CTL_CHECK; j++) {
ret_val = qla4_83xx_rd_reg_indirect(ha, ret_val = ha->isp_ops->rd_reg_indirect(ha,
MD_MIU_TEST_AGT_CTRL, MD_MIU_TEST_AGT_CTRL,
&agt_ctrl); &agt_ctrl);
if (ret_val == QLA_ERROR) { if (ret_val == QLA_ERROR) {
ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n", ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n",
__func__); __func__);
@ -760,7 +762,7 @@ static int qla4_83xx_copy_bootloader(struct scsi_qla_host *ha)
__func__)); __func__));
/* 128 bit/16 byte write to MS memory */ /* 128 bit/16 byte write to MS memory */
ret_val = qla4_83xx_ms_mem_write_128b(ha, dest, (uint32_t *)p_cache, ret_val = qla4_8xxx_ms_mem_write_128b(ha, dest, (uint32_t *)p_cache,
count); count);
if (ret_val == QLA_ERROR) { if (ret_val == QLA_ERROR) {
ql4_printk(KERN_ERR, ha, "%s: Error writing firmware to MS\n", ql4_printk(KERN_ERR, ha, "%s: Error writing firmware to MS\n",

2
drivers/scsi/qla4xxx/ql4_glbl.h
View File

@ -274,7 +274,7 @@ int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma, int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
uint32_t acb_type, uint32_t len); uint32_t acb_type, uint32_t len);
int qla4_84xx_config_acb(struct scsi_qla_host *ha, int acb_config); int qla4_84xx_config_acb(struct scsi_qla_host *ha, int acb_config);
int qla4_83xx_ms_mem_write_128b(struct scsi_qla_host *ha, int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha,
uint64_t addr, uint32_t *data, uint32_t count); uint64_t addr, uint32_t *data, uint32_t count);
uint8_t qla4xxx_set_ipaddr_state(uint8_t fw_ipaddr_state); uint8_t qla4xxx_set_ipaddr_state(uint8_t fw_ipaddr_state);
int qla4_83xx_get_port_config(struct scsi_qla_host *ha, uint32_t *config); int qla4_83xx_get_port_config(struct scsi_qla_host *ha, uint32_t *config);

15
drivers/scsi/qla4xxx/ql4_nx.c
View File

@ -1918,7 +1918,7 @@ static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha,
return rval; return rval;
} }
static int qla4_83xx_minidump_pex_dma_read(struct scsi_qla_host *ha, static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha,
struct qla8xxx_minidump_entry_hdr *entry_hdr, struct qla8xxx_minidump_entry_hdr *entry_hdr,
uint32_t **d_ptr) uint32_t **d_ptr)
{ {
@ -1995,7 +1995,7 @@ static int qla4_83xx_minidump_pex_dma_read(struct scsi_qla_host *ha,
dma_desc.cmd.read_data_size = size; dma_desc.cmd.read_data_size = size;
/* Prepare: Write pex-dma descriptor to MS memory. */ /* Prepare: Write pex-dma descriptor to MS memory. */
rval = qla4_83xx_ms_mem_write_128b(ha, rval = qla4_8xxx_ms_mem_write_128b(ha,
(uint64_t)m_hdr->desc_card_addr, (uint64_t)m_hdr->desc_card_addr,
(uint32_t *)&dma_desc, (uint32_t *)&dma_desc,
(sizeof(struct qla4_83xx_pex_dma_descriptor)/16)); (sizeof(struct qla4_83xx_pex_dma_descriptor)/16));
@ -2455,17 +2455,10 @@ static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
uint32_t *data_ptr = *d_ptr; uint32_t *data_ptr = *d_ptr;
int rval = QLA_SUCCESS; int rval = QLA_SUCCESS;
if (is_qla8032(ha) || is_qla8042(ha)) { rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr);
rval = qla4_83xx_minidump_pex_dma_read(ha, entry_hdr, if (rval != QLA_SUCCESS)
&data_ptr);
if (rval != QLA_SUCCESS) {
rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
&data_ptr);
}
} else {
rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
&data_ptr); &data_ptr);
}
*d_ptr = data_ptr; *d_ptr = data_ptr;
return rval; return rval;
} }