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drm/via: drop use of DRM(READ|WRITE) macros

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The DRM_READ, DRM_WRITE macros comes from the deprecated drm_os_linux.h
header file. Remove their use to remove this dependency.

Replace the use of the macros with static inline variants.

v4:
- Use a more standard via_write8_mask() function (Emil)

v3:
- Use static inline functions, rather than macros (Emil)
- Use dedicated mask variants for byte access (Emil)

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: Kevin Brace <kevinbrace@gmx.com>
Cc: Thomas Hellstrom <thellstrom@vmware.com>
Cc: "Gustavo A. R. Silva" <gustavo@embeddedor.com>
Cc: Mike Marshall <hubcap@omnibond.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Michel Dänzer <michel@daenzer.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20190723200944.17285-2-sam@ravnborg.org
This commit is contained in:
Sam Ravnborg 2019-07-23 22:09:41 +02:00
parent 17224cf29c
commit 3bf2a06e36
5 changed files with 83 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
drivers/gpu/drm/via/via_dma.c
View File

@ -430,14 +430,14 @@ static int via_hook_segment(drm_via_private_t *dev_priv,
diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
count = 10000000;
while (diff == 0 && count--) {
paused = (VIA_READ(0x41c) & 0x80000000);
paused = (via_read(dev_priv, 0x41c) & 0x80000000);
if (paused)
break;
reader = *(dev_priv->hw_addr_ptr);
diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
}
paused = VIA_READ(0x41c) & 0x80000000;
paused = via_read(dev_priv, 0x41c) & 0x80000000;
if (paused && !no_pci_fire) {
reader = *(dev_priv->hw_addr_ptr);
@ -454,10 +454,10 @@ static int via_hook_segment(drm_via_private_t *dev_priv,
* doesn't make a difference.
*/
VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
VIA_READ(VIA_REG_TRANSPACE);
via_write(dev_priv, VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_hi);
via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_lo);
via_read(dev_priv, VIA_REG_TRANSPACE);
}
}
return paused;
@ -467,10 +467,10 @@ static int via_wait_idle(drm_via_private_t *dev_priv)
{
int count = 10000000;
while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && --count)
while (!(via_read(dev_priv, VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && --count)
;
while (count && (VIA_READ(VIA_REG_STATUS) &
while (count && (via_read(dev_priv, VIA_REG_STATUS) &
(VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
VIA_3D_ENG_BUSY)))
--count;
@ -536,21 +536,21 @@ static void via_cmdbuf_start(drm_via_private_t *dev_priv)
via_flush_write_combine();
(void) *(volatile uint32_t *)dev_priv->last_pause_ptr;
VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
VIA_WRITE(VIA_REG_TRANSPACE, command);
VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
via_write(dev_priv, VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
via_write(dev_priv, VIA_REG_TRANSPACE, command);
via_write(dev_priv, VIA_REG_TRANSPACE, start_addr_lo);
via_write(dev_priv, VIA_REG_TRANSPACE, end_addr_lo);
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_hi);
via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_lo);
wmb();
VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
VIA_READ(VIA_REG_TRANSPACE);
via_write(dev_priv, VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
via_read(dev_priv, VIA_REG_TRANSPACE);
dev_priv->dma_diff = 0;
count = 10000000;
while (!(VIA_READ(0x41c) & 0x80000000) && count--);
while (!(via_read(dev_priv, 0x41c) & 0x80000000) && count--);
reader = *(dev_priv->hw_addr_ptr);
ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +

24
drivers/gpu/drm/via/via_dmablit.c
View File

@ -214,16 +214,16 @@ via_fire_dmablit(struct drm_device *dev, drm_via_sg_info_t *vsg, int engine)
{
drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
VIA_WRITE(VIA_PCI_DMA_MAR0 + engine*0x10, 0);
VIA_WRITE(VIA_PCI_DMA_DAR0 + engine*0x10, 0);
VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD |
via_write(dev_priv, VIA_PCI_DMA_MAR0 + engine*0x10, 0);
via_write(dev_priv, VIA_PCI_DMA_DAR0 + engine*0x10, 0);
via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD |
VIA_DMA_CSR_DE);
VIA_WRITE(VIA_PCI_DMA_MR0 + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE);
VIA_WRITE(VIA_PCI_DMA_BCR0 + engine*0x10, 0);
VIA_WRITE(VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start);
via_write(dev_priv, VIA_PCI_DMA_MR0 + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE);
via_write(dev_priv, VIA_PCI_DMA_BCR0 + engine*0x10, 0);
via_write(dev_priv, VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start);
wmb();
VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS);
VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04);
via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS);
via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04);
}
/*
@ -291,7 +291,7 @@ via_abort_dmablit(struct drm_device *dev, int engine)
{
drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA);
via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA);
}
static void
@ -299,7 +299,7 @@ via_dmablit_engine_off(struct drm_device *dev, int engine)
{
drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD);
via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD);
}
@ -330,7 +330,7 @@ via_dmablit_handler(struct drm_device *dev, int engine, int from_irq)
spin_lock_irqsave(&blitq->blit_lock, irqsave);
done_transfer = blitq->is_active &&
((status = VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD);
((status = via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD);
done_transfer = done_transfer || (blitq->aborting && !(status & VIA_DMA_CSR_DE));
cur = blitq->cur;
@ -349,7 +349,7 @@ via_dmablit_handler(struct drm_device *dev, int engine, int from_irq)
* Clear transfer done flag.
*/
VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD);
via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD);
blitq->is_active = 0;
blitq->aborting = 0;

30
drivers/gpu/drm/via/via_drv.h
View File

@ -113,12 +113,32 @@ enum via_family {
};
/* VIA MMIO register access */
#define VIA_BASE ((dev_priv->mmio))
static inline u32 via_read(struct drm_via_private *dev_priv, u32 reg)
{
return readl((void __iomem *)(dev_priv->mmio->handle + reg));
}
#define VIA_READ(reg) DRM_READ32(VIA_BASE, reg)
#define VIA_WRITE(reg, val) DRM_WRITE32(VIA_BASE, reg, val)
#define VIA_READ8(reg) DRM_READ8(VIA_BASE, reg)
#define VIA_WRITE8(reg, val) DRM_WRITE8(VIA_BASE, reg, val)
static inline void via_write(struct drm_via_private *dev_priv, u32 reg,
u32 val)
{
writel(val, (void __iomem *)(dev_priv->mmio->handle + reg));
}
static inline void via_write8(struct drm_via_private *dev_priv, u32 reg,
u32 val)
{
writeb(val, (void __iomem *)(dev_priv->mmio->handle + reg));
}
static inline void via_write8_mask(struct drm_via_private *dev_priv,
u32 reg, u32 mask, u32 val)
{
u32 tmp;
tmp = readb((void __iomem *)(dev_priv->mmio->handle + reg));
tmp = (tmp & ~mask) | (val & mask);
writeb(tmp, (void __iomem *)(dev_priv->mmio->handle + reg));
}
extern const struct drm_ioctl_desc via_ioctls[];
extern int via_max_ioctl;

46
drivers/gpu/drm/via/via_irq.c
View File

@ -108,7 +108,7 @@ irqreturn_t via_driver_irq_handler(int irq, void *arg)
drm_via_irq_t *cur_irq = dev_priv->via_irqs;
int i;
status = VIA_READ(VIA_REG_INTERRUPT);
status = via_read(dev_priv, VIA_REG_INTERRUPT);
if (status & VIA_IRQ_VBLANK_PENDING) {
atomic_inc(&dev_priv->vbl_received);
if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {
@ -143,7 +143,7 @@ irqreturn_t via_driver_irq_handler(int irq, void *arg)
}
/* Acknowledge interrupts */
VIA_WRITE(VIA_REG_INTERRUPT, status);
via_write(dev_priv, VIA_REG_INTERRUPT, status);
if (handled)
@ -158,8 +158,8 @@ static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t *dev_priv)
if (dev_priv) {
/* Acknowledge interrupts */
status = VIA_READ(VIA_REG_INTERRUPT);
VIA_WRITE(VIA_REG_INTERRUPT, status |
status = via_read(dev_priv, VIA_REG_INTERRUPT);
via_write(dev_priv, VIA_REG_INTERRUPT, status |
dev_priv->irq_pending_mask);
}
}
@ -174,11 +174,11 @@ int via_enable_vblank(struct drm_device *dev, unsigned int pipe)
return -EINVAL;
}
status = VIA_READ(VIA_REG_INTERRUPT);
VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE);
status = via_read(dev_priv, VIA_REG_INTERRUPT);
via_write(dev_priv, VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE);
VIA_WRITE8(0x83d4, 0x11);
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
via_write8(dev_priv, 0x83d4, 0x11);
via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30);
return 0;
}
@ -188,11 +188,11 @@ void via_disable_vblank(struct drm_device *dev, unsigned int pipe)
drm_via_private_t *dev_priv = dev->dev_private;
u32 status;
status = VIA_READ(VIA_REG_INTERRUPT);
VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE);
status = via_read(dev_priv, VIA_REG_INTERRUPT);
via_write(dev_priv, VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE);
VIA_WRITE8(0x83d4, 0x11);
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
via_write8(dev_priv, 0x83d4, 0x11);
via_write8_mask(dev_priv, 0x83d5, 0x30, 0);
if (pipe != 0)
DRM_ERROR("%s: bad crtc %u\n", __func__, pipe);
@ -234,7 +234,7 @@ via_driver_irq_wait(struct drm_device *dev, unsigned int irq, int force_sequence
if (masks[real_irq][2] && !force_sequence) {
DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) ==
masks[irq][4]));
cur_irq_sequence = atomic_read(&cur_irq->irq_received);
} else {
@ -292,8 +292,8 @@ void via_driver_irq_preinstall(struct drm_device *dev)
dev_priv->last_vblank_valid = 0;
/* Clear VSync interrupt regs */
status = VIA_READ(VIA_REG_INTERRUPT);
VIA_WRITE(VIA_REG_INTERRUPT, status &
status = via_read(dev_priv, VIA_REG_INTERRUPT);
via_write(dev_priv, VIA_REG_INTERRUPT, status &
~(dev_priv->irq_enable_mask));
/* Clear bits if they're already high */
@ -310,13 +310,13 @@ int via_driver_irq_postinstall(struct drm_device *dev)
if (!dev_priv)
return -EINVAL;
status = VIA_READ(VIA_REG_INTERRUPT);
VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
status = via_read(dev_priv, VIA_REG_INTERRUPT);
via_write(dev_priv, VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
| dev_priv->irq_enable_mask);
/* Some magic, oh for some data sheets ! */
VIA_WRITE8(0x83d4, 0x11);
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
via_write8(dev_priv, 0x83d4, 0x11);
via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30);
return 0;
}
@ -331,11 +331,11 @@ void via_driver_irq_uninstall(struct drm_device *dev)
/* Some more magic, oh for some data sheets ! */
VIA_WRITE8(0x83d4, 0x11);
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
via_write8(dev_priv, 0x83d4, 0x11);
via_write8_mask(dev_priv, 0x83d5, 0x30, 0);
status = VIA_READ(VIA_REG_INTERRUPT);
VIA_WRITE(VIA_REG_INTERRUPT, status &
status = via_read(dev_priv, VIA_REG_INTERRUPT);
via_write(dev_priv, VIA_REG_INTERRUPT, status &
~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
}
}

12
drivers/gpu/drm/via/via_verifier.c
View File

@ -725,14 +725,14 @@ via_parse_header2(drm_via_private_t *dev_priv, uint32_t const **buffer,
next_fire = dev_priv->fire_offsets[*fire_count];
buf++;
cmd = (*buf & 0xFFFF0000) >> 16;
VIA_WRITE(HC_REG_TRANS_SET + HC_REG_BASE, *buf++);
via_write(dev_priv, HC_REG_TRANS_SET + HC_REG_BASE, *buf++);
switch (cmd) {
case HC_ParaType_CmdVdata:
while ((buf < buf_end) &&
(*fire_count < dev_priv->num_fire_offsets) &&
(*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB) {
while (buf <= next_fire) {
VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
via_write(dev_priv, HC_REG_TRANS_SPACE + HC_REG_BASE +
(burst & 63), *buf++);
burst += 4;
}
@ -753,7 +753,7 @@ via_parse_header2(drm_via_private_t *dev_priv, uint32_t const **buffer,
(*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
break;
VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
via_write(dev_priv, HC_REG_TRANS_SPACE + HC_REG_BASE +
(burst & 63), *buf++);
burst += 4;
}
@ -843,7 +843,7 @@ via_parse_header1(drm_via_private_t *dev_priv, uint32_t const **buffer,
cmd = *buf;
if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
break;
VIA_WRITE((cmd & ~HALCYON_HEADER1MASK) << 2, *++buf);
via_write(dev_priv, (cmd & ~HALCYON_HEADER1MASK) << 2, *++buf);
buf++;
}
*buffer = buf;
@ -894,7 +894,7 @@ via_parse_vheader5(drm_via_private_t *dev_priv, uint32_t const **buffer,
i = count = *buf;
buf += 3;
while (i--)
VIA_WRITE(addr, *buf++);
via_write(dev_priv, addr, *buf++);
if (count & 3)
buf += 4 - (count & 3);
*buffer = buf;
@ -950,7 +950,7 @@ via_parse_vheader6(drm_via_private_t *dev_priv, uint32_t const **buffer,
buf += 3;
while (i--) {
addr = *buf++;
VIA_WRITE(addr, *buf++);
via_write(dev_priv, addr, *buf++);
}
count <<= 1;
if (count & 3)