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KVM: SVM: Add intercept check for accessing dr registers
This patch adds the intercept checks for instruction accessing the debug registers. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@redhat.com>
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@ -309,6 +309,8 @@ enum x86_intercept {
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x86_intercept_clts,
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x86_intercept_lmsw,
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x86_intercept_smsw,
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x86_intercept_dr_read,
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x86_intercept_dr_write,
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x86_intercept_lidt,
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x86_intercept_sidt,
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x86_intercept_lgdt,
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@ -509,6 +509,11 @@ static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
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return X86EMUL_PROPAGATE_FAULT;
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}
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static int emulate_db(struct x86_emulate_ctxt *ctxt)
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{
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return emulate_exception(ctxt, DB_VECTOR, 0, false);
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}
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static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
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{
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return emulate_exception(ctxt, GP_VECTOR, err, true);
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@ -2534,6 +2539,47 @@ static int check_cr_write(struct x86_emulate_ctxt *ctxt)
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return X86EMUL_CONTINUE;
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}
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static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
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{
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unsigned long dr7;
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ctxt->ops->get_dr(7, &dr7, ctxt->vcpu);
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/* Check if DR7.Global_Enable is set */
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return dr7 & (1 << 13);
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}
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static int check_dr_read(struct x86_emulate_ctxt *ctxt)
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{
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struct decode_cache *c = &ctxt->decode;
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int dr = c->modrm_reg;
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u64 cr4;
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if (dr > 7)
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return emulate_ud(ctxt);
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cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
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if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
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return emulate_ud(ctxt);
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if (check_dr7_gd(ctxt))
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return emulate_db(ctxt);
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return X86EMUL_CONTINUE;
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}
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static int check_dr_write(struct x86_emulate_ctxt *ctxt)
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{
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struct decode_cache *c = &ctxt->decode;
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u64 new_val = c->src.val64;
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int dr = c->modrm_reg;
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if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
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return emulate_gp(ctxt, 0);
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return check_dr_read(ctxt);
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}
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#define D(_y) { .flags = (_y) }
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#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
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#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
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@ -2728,9 +2774,9 @@ static struct opcode twobyte_table[256] = {
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N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
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/* 0x20 - 0x2F */
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DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
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D(ModRM | DstMem | Priv | Op3264),
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DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
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DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
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D(ModRM | SrcMem | Priv | Op3264),
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DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
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N, N, N, N,
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N, N, N, N, N, N, N, N,
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/* 0x30 - 0x3F */
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@ -3818,12 +3864,6 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
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c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
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break;
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case 0x21: /* mov from dr to reg */
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if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
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(c->modrm_reg == 4 || c->modrm_reg == 5)) {
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emulate_ud(ctxt);
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rc = X86EMUL_PROPAGATE_FAULT;
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goto done;
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}
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ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
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break;
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case 0x22: /* mov reg, cr */
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@ -3835,13 +3875,6 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
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c->dst.type = OP_NONE;
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break;
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case 0x23: /* mov from reg to dr */
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if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
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(c->modrm_reg == 4 || c->modrm_reg == 5)) {
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emulate_ud(ctxt);
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rc = X86EMUL_PROPAGATE_FAULT;
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goto done;
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}
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if (ops->set_dr(c->modrm_reg, c->src.val &
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((ctxt->mode == X86EMUL_MODE_PROT64) ?
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~0ULL : ~0U), ctxt->vcpu) < 0) {
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@ -3882,6 +3882,8 @@ static struct __x86_intercept {
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[x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
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[x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
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[x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
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[x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
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[x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
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};
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#undef POST_EX
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@ -3939,6 +3941,10 @@ static int svm_check_intercept(struct kvm_vcpu *vcpu,
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break;
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}
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case SVM_EXIT_READ_DR0:
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case SVM_EXIT_WRITE_DR0:
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icpt_info.exit_code += info->modrm_reg;
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break;
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default:
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break;
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}
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