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mtd: spi-nor: remove micron_quad_enable()
This patch remove the micron_quad_enable() function which force the Quad
SPI mode. However, once this mode is enabled, the Micron memory expect ALL
commands to use the SPI 4-4-4 protocol. Hence a failure does occur when
calling spi_nor_wait_till_ready() right after the update of the Enhanced
Volatile Configuration Register (EVCR) in the micron_quad_enable() as
the SPI controller driver is not aware about the protocol change.
Since there is almost no performance increase using Fast Read 4-4-4
commands instead of Fast Read 1-1-4 commands, we rather keep on using the
Extended SPI mode than enabling the Quad SPI mode.
Let's take the example of the pretty standard use of 8 dummy cycles during
Fast Read operations on 64KB erase sectors:
Fast Read 1-1-4 requires 8 cycles for the command, then 24 cycles for the
3byte address followed by 8 dummy clock cycles and finally 65536*2 cycles
for the read data; so 131112 clock cycles.
On the other hand the Fast Read 4-4-4 would require 2 cycles for the
command, then 6 cycles for the 3byte address followed by 8 dummy clock
cycles and finally 65536*2 cycles for the read data. So 131088 clock
cycles. The theorical bandwidth increase is 0.0%.
Now using Fast Read operations on 512byte pages:
Fast Read 1-1-4 needs 8+24+8+(512*2) = 1064 clock cycles whereas Fast
Read 4-4-4 would requires 2+6+8+(512*2) = 1040 clock cycles. Hence the
theorical bandwidth increase is 2.3%.
Consecutive reads for non sequential pages is not a relevant use case so
The Quad SPI mode is not worth it.
mtd_speedtest seems to confirm these figures.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Fixes: 548cd3ab54
("mtd: spi-nor: Add quad I/O support for Micron SPI NOR")
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
parent
c082667949
commit
3b5394a3cc
@ -1101,45 +1101,6 @@ static int spansion_quad_enable(struct spi_nor *nor)
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return 0;
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}
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static int micron_quad_enable(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
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if (ret < 0) {
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dev_err(nor->dev, "error %d reading EVCR\n", ret);
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return ret;
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}
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write_enable(nor);
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/* set EVCR, enable quad I/O */
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nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
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ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1);
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if (ret < 0) {
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dev_err(nor->dev, "error while writing EVCR register\n");
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return ret;
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}
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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return ret;
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/* read EVCR and check it */
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ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
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if (ret < 0) {
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dev_err(nor->dev, "error %d reading EVCR\n", ret);
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return ret;
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}
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if (val & EVCR_QUAD_EN_MICRON) {
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dev_err(nor->dev, "Micron EVCR Quad bit not clear\n");
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return -EINVAL;
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}
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return 0;
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}
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static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
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{
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int status;
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@ -1153,12 +1114,7 @@ static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
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}
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return status;
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case SNOR_MFR_MICRON:
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status = micron_quad_enable(nor);
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if (status) {
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dev_err(nor->dev, "Micron quad-read not enabled\n");
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return -EINVAL;
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}
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return status;
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return 0;
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default:
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status = spansion_quad_enable(nor);
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if (status) {
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