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staging: comedi: addi_eeprom: remove source file
This source file is no longer included by any of the addi-data drivers. Remove it. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
715ce8aac4
commit
3b00a0e0d6
@ -1,360 +0,0 @@
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/*
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* addi_eeprom.c - ADDI EEPROM Module
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* Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
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* Project manager: Eric Stolz
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*
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* ADDI-DATA GmbH
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* Dieselstrasse 3
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* D-77833 Ottersweier
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* Tel: +19(0)7223/9493-0
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* Fax: +49(0)7223/9493-92
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* http://www.addi-data.com
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* info@addi-data.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <linux/delay.h>
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#define NVRAM_USER_DATA_START 0x100
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#define NVCMD_BEGIN_READ (0x7 << 5) /* nvRam begin read command */
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#define NVCMD_LOAD_LOW (0x4 << 5) /* nvRam load low command */
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#define NVCMD_LOAD_HIGH (0x5 << 5) /* nvRam load high command */
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#define EE93C76_CLK_BIT (1 << 0)
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#define EE93C76_CS_BIT (1 << 1)
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#define EE93C76_DOUT_BIT (1 << 2)
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#define EE93C76_DIN_BIT (1 << 3)
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#define EE93C76_READ_CMD (0x0180 << 4)
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#define EE93C76_CMD_LEN 13
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#define EEPROM_DIGITALINPUT 0
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#define EEPROM_DIGITALOUTPUT 1
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#define EEPROM_ANALOGINPUT 2
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#define EEPROM_ANALOGOUTPUT 3
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#define EEPROM_TIMER 4
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#define EEPROM_WATCHDOG 5
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#define EEPROM_TIMER_WATCHDOG_COUNTER 10
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static void addi_eeprom_clk_93c76(unsigned long iobase, unsigned int val)
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{
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outl(val & ~EE93C76_CLK_BIT, iobase);
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udelay(100);
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outl(val | EE93C76_CLK_BIT, iobase);
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udelay(100);
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}
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static unsigned int addi_eeprom_cmd_93c76(unsigned long iobase,
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unsigned int cmd,
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unsigned char len)
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{
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unsigned int val = EE93C76_CS_BIT;
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int i;
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/* Toggle EEPROM's Chip select to get it out of Shift Register Mode */
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outl(val, iobase);
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udelay(100);
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/* Send EEPROM command - one bit at a time */
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for (i = (len - 1); i >= 0; i--) {
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if (cmd & (1 << i))
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val |= EE93C76_DOUT_BIT;
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else
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val &= ~EE93C76_DOUT_BIT;
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/* Write the command */
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outl(val, iobase);
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udelay(100);
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addi_eeprom_clk_93c76(iobase, val);
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}
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return val;
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}
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static unsigned short addi_eeprom_readw_93c76(unsigned long iobase,
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unsigned short addr)
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{
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unsigned short val = 0;
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unsigned int cmd;
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unsigned int tmp;
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int i;
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/* Send EEPROM read command and offset to EEPROM */
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cmd = EE93C76_READ_CMD | (addr / 2);
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cmd = addi_eeprom_cmd_93c76(iobase, cmd, EE93C76_CMD_LEN);
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/* Get the 16-bit value */
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for (i = 0; i < 16; i++) {
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addi_eeprom_clk_93c76(iobase, cmd);
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tmp = inl(iobase);
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udelay(100);
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val <<= 1;
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if (tmp & EE93C76_DIN_BIT)
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val |= 0x1;
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}
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/* Toggle EEPROM's Chip select to get it out of Shift Register Mode */
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outl(0, iobase);
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udelay(100);
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return val;
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}
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static void addi_eeprom_nvram_wait(unsigned long iobase)
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{
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unsigned char val;
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do {
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val = inb(iobase + AMCC_OP_REG_MCSR_NVCMD);
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} while (val & 0x80);
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}
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static unsigned short addi_eeprom_readw_nvram(unsigned long iobase,
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unsigned short addr)
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{
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unsigned short val = 0;
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unsigned char tmp;
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unsigned char i;
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for (i = 0; i < 2; i++) {
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/* Load the low 8 bit address */
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outb(NVCMD_LOAD_LOW, iobase + AMCC_OP_REG_MCSR_NVCMD);
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addi_eeprom_nvram_wait(iobase);
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outb((addr + i) & 0xff, iobase + AMCC_OP_REG_MCSR_NVDATA);
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addi_eeprom_nvram_wait(iobase);
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/* Load the high 8 bit address */
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outb(NVCMD_LOAD_HIGH, iobase + AMCC_OP_REG_MCSR_NVCMD);
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addi_eeprom_nvram_wait(iobase);
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outb(((addr + i) >> 8) & 0xff,
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iobase + AMCC_OP_REG_MCSR_NVDATA);
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addi_eeprom_nvram_wait(iobase);
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/* Read the eeprom data byte */
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outb(NVCMD_BEGIN_READ, iobase + AMCC_OP_REG_MCSR_NVCMD);
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addi_eeprom_nvram_wait(iobase);
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tmp = inb(iobase + AMCC_OP_REG_MCSR_NVDATA);
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addi_eeprom_nvram_wait(iobase);
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if (i == 0)
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val |= tmp;
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else
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val |= (tmp << 8);
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}
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return val;
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}
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static unsigned short addi_eeprom_readw(unsigned long iobase,
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char *type,
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unsigned short addr)
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{
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unsigned short val = 0;
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/* Add the offset to the start of the user data */
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addr += NVRAM_USER_DATA_START;
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if (!strcmp(type, "S5920") || !strcmp(type, "S5933"))
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val = addi_eeprom_readw_nvram(iobase, addr);
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if (!strcmp(type, "93C76"))
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val = addi_eeprom_readw_93c76(iobase, addr);
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return val;
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}
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static void addi_eeprom_read_di_info(struct comedi_device *dev,
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unsigned long iobase,
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unsigned short addr)
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{
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const struct addi_board *this_board = dev->board_ptr;
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struct addi_private *devpriv = dev->private;
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char *type = this_board->pc_EepromChip;
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unsigned short tmp;
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/* Number of channels */
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tmp = addi_eeprom_readw(iobase, type, addr + 6);
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devpriv->s_EeParameters.i_NbrDiChannel = tmp;
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/* Interruptible or not */
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tmp = addi_eeprom_readw(iobase, type, addr + 8);
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tmp = (tmp >> 7) & 0x01;
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/* How many interruptible logic */
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tmp = addi_eeprom_readw(iobase, type, addr + 10);
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}
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static void addi_eeprom_read_do_info(struct comedi_device *dev,
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unsigned long iobase,
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unsigned short addr)
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{
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const struct addi_board *this_board = dev->board_ptr;
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struct addi_private *devpriv = dev->private;
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char *type = this_board->pc_EepromChip;
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unsigned short tmp;
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/* Number of channels */
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tmp = addi_eeprom_readw(iobase, type, addr + 6);
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devpriv->s_EeParameters.i_NbrDoChannel = tmp;
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devpriv->s_EeParameters.i_DoMaxdata = 0xffffffff >> (32 - tmp);
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}
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static void addi_eeprom_read_timer_info(struct comedi_device *dev,
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unsigned long iobase,
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unsigned short addr)
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{
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struct addi_private *devpriv = dev->private;
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#if 0
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const struct addi_board *this_board = dev->board_ptr;
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char *type = this_board->pc_EepromChip;
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unsigned short offset = 0;
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unsigned short ntimers;
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unsigned short tmp;
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int i;
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/* Number of Timers */
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ntimers = addi_eeprom_readw(iobase, type, addr + 6);
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/* Read header size */
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for (i = 0; i < ntimers; i++) {
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unsigned short size;
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unsigned short res;
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unsigned short mode;
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unsigned short min_timing;
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unsigned short timebase;
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size = addi_eeprom_readw(iobase, type, addr + 8 + offset + 0);
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/* Resolution / Mode */
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tmp = addi_eeprom_readw(iobase, type, addr + 8 + offset + 2);
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res = (tmp >> 10) & 0x3f;
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mode = (tmp >> 4) & 0x3f;
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/* MinTiming / Timebase */
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tmp = addi_eeprom_readw(iobase, type, addr + 8 + offset + 4);
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min_timing = (tmp >> 6) & 0x3ff;
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Timebase = tmp & 0x3f;
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offset += size;
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}
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#endif
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/* Timer subdevice present */
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devpriv->s_EeParameters.i_Timer = 1;
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}
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static void addi_eeprom_read_ao_info(struct comedi_device *dev,
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unsigned long iobase,
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unsigned short addr)
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{
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const struct addi_board *this_board = dev->board_ptr;
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struct addi_private *devpriv = dev->private;
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char *type = this_board->pc_EepromChip;
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unsigned short tmp;
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/* No of channels for 1st hard component */
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tmp = addi_eeprom_readw(iobase, type, addr + 10);
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devpriv->s_EeParameters.i_NbrAoChannel = (tmp >> 4) & 0x3ff;
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/* Resolution for 1st hard component */
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tmp = addi_eeprom_readw(iobase, type, addr + 16);
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tmp = (tmp >> 8) & 0xff;
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devpriv->s_EeParameters.i_AoMaxdata = 0xfff >> (16 - tmp);
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}
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static void addi_eeprom_read_ai_info(struct comedi_device *dev,
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unsigned long iobase,
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unsigned short addr)
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{
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const struct addi_board *this_board = dev->board_ptr;
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struct addi_private *devpriv = dev->private;
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char *type = this_board->pc_EepromChip;
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unsigned short offset;
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unsigned short tmp;
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/* No of channels for 1st hard component */
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tmp = addi_eeprom_readw(iobase, type, addr + 10);
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devpriv->s_EeParameters.i_NbrAiChannel = (tmp >> 4) & 0x3ff;
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if (!strcmp(dev->board_name, "apci3200"))
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devpriv->s_EeParameters.i_NbrAiChannel *= 4;
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tmp = addi_eeprom_readw(iobase, type, addr + 16);
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devpriv->s_EeParameters.ui_MinAcquisitiontimeNs = tmp * 1000;
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tmp = addi_eeprom_readw(iobase, type, addr + 30);
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devpriv->s_EeParameters.ui_MinDelaytimeNs = tmp * 1000;
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tmp = addi_eeprom_readw(iobase, type, addr + 20);
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/* dma = (tmp >> 13) & 0x01; */
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tmp = addi_eeprom_readw(iobase, type, addr + 72) & 0xff;
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if (tmp) { /* > 0 */
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/* offset of first analog input single header */
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offset = 74 + (2 * tmp) + (10 * (1 + (tmp / 16)));
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} else { /* = 0 */
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offset = 74;
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}
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/* Resolution */
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tmp = addi_eeprom_readw(iobase, type, addr + offset + 2) & 0x1f;
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devpriv->s_EeParameters.i_AiMaxdata = 0xffff >> (16 - tmp);
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}
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static void addi_eeprom_read_info(struct comedi_device *dev,
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unsigned long iobase)
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{
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const struct addi_board *this_board = dev->board_ptr;
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char *type = this_board->pc_EepromChip;
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unsigned short size;
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unsigned char nfuncs;
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int i;
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size = addi_eeprom_readw(iobase, type, 8);
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nfuncs = addi_eeprom_readw(iobase, type, 10) & 0xff;
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/* Read functionality details */
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for (i = 0; i < nfuncs; i++) {
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unsigned short offset = i * 4;
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unsigned short addr;
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unsigned char func;
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func = addi_eeprom_readw(iobase, type, 12 + offset) & 0x3f;
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addr = addi_eeprom_readw(iobase, type, 14 + offset);
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switch (func) {
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case EEPROM_DIGITALINPUT:
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addi_eeprom_read_di_info(dev, iobase, addr);
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break;
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case EEPROM_DIGITALOUTPUT:
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addi_eeprom_read_do_info(dev, iobase, addr);
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break;
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case EEPROM_ANALOGINPUT:
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addi_eeprom_read_ai_info(dev, iobase, addr);
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break;
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case EEPROM_ANALOGOUTPUT:
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addi_eeprom_read_ao_info(dev, iobase, addr);
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break;
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case EEPROM_TIMER:
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case EEPROM_WATCHDOG:
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case EEPROM_TIMER_WATCHDOG_COUNTER:
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addi_eeprom_read_timer_info(dev, iobase, addr);
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break;
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}
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}
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}
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