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pinctrl: sh-pfc: r8a77970: Add QSPI pins, groups, and functions
Add the QSPI{0|1} pins/groups/functions to the R8A77970 PFC driver. [Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/ SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to be in the alphanumeric order, removed unneeded empty lines, renamed the patch.] Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -1382,6 +1382,56 @@ static const unsigned int pwm4_b_mux[] = {
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PWM4_B_MARK,
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};
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/* - QSPI0 ------------------------------------------------------------------ */
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static const unsigned int qspi0_ctrl_pins[] = {
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/* SPCLK, SSL */
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RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
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};
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static const unsigned int qspi0_ctrl_mux[] = {
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QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
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};
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static const unsigned int qspi0_data2_pins[] = {
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/* MOSI_IO0, MISO_IO1 */
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RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
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};
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static const unsigned int qspi0_data2_mux[] = {
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QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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};
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static const unsigned int qspi0_data4_pins[] = {
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/* MOSI_IO0, MISO_IO1, IO2, IO3 */
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RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
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RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
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};
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static const unsigned int qspi0_data4_mux[] = {
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QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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QSPI0_IO2_MARK, QSPI0_IO3_MARK
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};
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/* - QSPI1 ------------------------------------------------------------------ */
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static const unsigned int qspi1_ctrl_pins[] = {
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/* SPCLK, SSL */
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RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
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};
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static const unsigned int qspi1_ctrl_mux[] = {
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QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
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};
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static const unsigned int qspi1_data2_pins[] = {
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/* MOSI_IO0, MISO_IO1 */
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RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
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};
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static const unsigned int qspi1_data2_mux[] = {
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QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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};
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static const unsigned int qspi1_data4_pins[] = {
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/* MOSI_IO0, MISO_IO1, IO2, IO3 */
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RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
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RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
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};
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static const unsigned int qspi1_data4_mux[] = {
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QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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QSPI1_IO2_MARK, QSPI1_IO3_MARK
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};
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/* - SCIF Clock ------------------------------------------------------------- */
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static const unsigned int scif_clk_a_pins[] = {
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/* SCIF_CLK */
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@ -1756,6 +1806,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(pwm3_b),
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SH_PFC_PIN_GROUP(pwm4_a),
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SH_PFC_PIN_GROUP(pwm4_b),
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SH_PFC_PIN_GROUP(qspi0_ctrl),
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SH_PFC_PIN_GROUP(qspi0_data2),
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SH_PFC_PIN_GROUP(qspi0_data4),
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SH_PFC_PIN_GROUP(qspi1_ctrl),
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SH_PFC_PIN_GROUP(qspi1_data2),
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SH_PFC_PIN_GROUP(qspi1_data4),
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SH_PFC_PIN_GROUP(scif_clk_a),
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SH_PFC_PIN_GROUP(scif_clk_b),
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SH_PFC_PIN_GROUP(scif0_data),
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@ -1950,6 +2006,18 @@ static const char * const pwm4_groups[] = {
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"pwm4_b",
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};
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static const char * const qspi0_groups[] = {
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"qspi0_ctrl",
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"qspi0_data2",
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"qspi0_data4",
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};
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static const char * const qspi1_groups[] = {
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"qspi1_ctrl",
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"qspi1_data2",
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"qspi1_data4",
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};
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static const char * const scif_clk_groups[] = {
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"scif_clk_a",
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"scif_clk_b",
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@ -2033,6 +2101,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(pwm2),
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SH_PFC_FUNCTION(pwm3),
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SH_PFC_FUNCTION(pwm4),
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SH_PFC_FUNCTION(qspi0),
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SH_PFC_FUNCTION(qspi1),
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SH_PFC_FUNCTION(scif_clk),
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SH_PFC_FUNCTION(scif0),
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SH_PFC_FUNCTION(scif1),
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