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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ARM: shmobile: r8a7790: Add DU node to device tree
Add the DU device with a disabled state. Boards that want to enable the DU need to specify the output topology. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> [horms+renesas@verge.net.au: resolved minor conflict] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -600,6 +600,96 @@ vin3: video@e6ef3000 {
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status = "disabled";
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};
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vsp1@fe920000 {
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compatible = "renesas,vsp1";
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reg = <0 0xfe920000 0 0x8000>;
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interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
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renesas,has-sru;
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renesas,#rpf = <5>;
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renesas,#uds = <1>;
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renesas,#wpf = <4>;
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};
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vsp1@fe928000 {
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compatible = "renesas,vsp1";
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reg = <0 0xfe928000 0 0x8000>;
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interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
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renesas,has-lut;
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renesas,has-sru;
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renesas,#rpf = <5>;
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renesas,#uds = <3>;
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renesas,#wpf = <4>;
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};
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vsp1@fe930000 {
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compatible = "renesas,vsp1";
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reg = <0 0xfe930000 0 0x8000>;
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interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
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renesas,has-lif;
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renesas,has-lut;
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renesas,#rpf = <4>;
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renesas,#uds = <1>;
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renesas,#wpf = <4>;
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};
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vsp1@fe938000 {
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compatible = "renesas,vsp1";
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reg = <0 0xfe938000 0 0x8000>;
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interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
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renesas,has-lif;
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renesas,has-lut;
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renesas,#rpf = <4>;
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renesas,#uds = <1>;
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renesas,#wpf = <4>;
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};
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du: display@feb00000 {
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compatible = "renesas,du-r8a7790";
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reg = <0 0xfeb00000 0 0x70000>,
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<0 0xfeb90000 0 0x1c>,
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<0 0xfeb94000 0 0x1c>;
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reg-names = "du", "lvds.0", "lvds.1";
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interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
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<0 268 IRQ_TYPE_LEVEL_HIGH>,
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<0 269 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7790_CLK_DU0>,
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<&mstp7_clks R8A7790_CLK_DU1>,
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<&mstp7_clks R8A7790_CLK_DU2>,
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<&mstp7_clks R8A7790_CLK_LVDS0>,
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<&mstp7_clks R8A7790_CLK_LVDS1>;
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clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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du_out_rgb: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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du_out_lvds0: endpoint {
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};
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};
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port@2 {
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reg = <2>;
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du_out_lvds1: endpoint {
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};
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};
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};
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};
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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