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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 18:27:14 +07:00
habanalabs: configure maximum queues per asic
Currently the amount of maximum queues is statically configured. Using a static value is causing redundunt cycles when traversing all queues and consumes more memory than actually needed. In this patch we configure each asic with the exact number of queues needed. Signed-off-by: Ofir Bitton <obitton@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
This commit is contained in:
Ofir Bitton
Oded Gabbay
parent
12ae3133d2
commit
3abc99bb7d
@ -363,6 +363,7 @@ static void cs_do_release(struct kref *ref)
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cs_counters_aggregate(hdev, cs->ctx);
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kfree(cs->jobs_in_queue_cnt);
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kfree(cs);
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}
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@ -435,13 +436,19 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx,
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other = ctx->cs_pending[cs_cmpl->cs_seq &
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(hdev->asic_prop.max_pending_cs - 1)];
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if ((other) && (!dma_fence_is_signaled(other))) {
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spin_unlock(&ctx->cs_lock);
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dev_dbg(hdev->dev,
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"Rejecting CS because of too many in-flights CS\n");
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rc = -EAGAIN;
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goto free_fence;
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}
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cs->jobs_in_queue_cnt = kcalloc(hdev->asic_prop.max_queues,
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sizeof(*cs->jobs_in_queue_cnt), GFP_ATOMIC);
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if (!cs->jobs_in_queue_cnt) {
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rc = -ENOMEM;
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goto free_fence;
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}
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dma_fence_init(&cs_cmpl->base_fence, &hl_fence_ops, &cs_cmpl->lock,
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ctx->asid, ctx->cs_sequence);
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@ -463,6 +470,7 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx,
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return 0;
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free_fence:
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spin_unlock(&ctx->cs_lock);
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kfree(cs_cmpl);
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free_cs:
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kfree(cs);
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@ -515,10 +523,18 @@ static int validate_queue_index(struct hl_device *hdev,
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struct asic_fixed_properties *asic = &hdev->asic_prop;
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struct hw_queue_properties *hw_queue_prop;
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/* This must be checked here to prevent out-of-bounds access to
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* hw_queues_props array
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*/
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if (chunk->queue_index >= asic->max_queues) {
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dev_err(hdev->dev, "Queue index %d is invalid\n",
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chunk->queue_index);
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return -EINVAL;
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}
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hw_queue_prop = &asic->hw_queues_props[chunk->queue_index];
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if ((chunk->queue_index >= HL_MAX_QUEUES) ||
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(hw_queue_prop->type == QUEUE_TYPE_NA)) {
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if (hw_queue_prop->type == QUEUE_TYPE_NA) {
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dev_err(hdev->dev, "Queue index %d is invalid\n",
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chunk->queue_index);
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return -EINVAL;
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@ -795,7 +811,7 @@ static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type,
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hw_queue_prop = &hdev->asic_prop.hw_queues_props[q_idx];
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q_type = hw_queue_prop->type;
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if ((q_idx >= HL_MAX_QUEUES) ||
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if ((q_idx >= hdev->asic_prop.max_queues) ||
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(!hw_queue_prop->supports_sync_stream)) {
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dev_err(hdev->dev, "Queue index %d is invalid\n", q_idx);
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rc = -EINVAL;
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@ -340,14 +340,15 @@ static int gaudi_get_fixed_properties(struct hl_device *hdev)
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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int i;
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if (GAUDI_QUEUE_ID_SIZE >= HL_MAX_QUEUES) {
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dev_err(hdev->dev,
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"Number of H/W queues must be smaller than %d\n",
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HL_MAX_QUEUES);
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return -EFAULT;
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}
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prop->max_queues = GAUDI_QUEUE_ID_SIZE;
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prop->hw_queues_props = kcalloc(prop->max_queues,
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sizeof(struct hw_queue_properties),
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GFP_KERNEL);
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for (i = 0 ; i < GAUDI_QUEUE_ID_SIZE ; i++) {
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if (!prop->hw_queues_props)
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return -ENOMEM;
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for (i = 0 ; i < prop->max_queues ; i++) {
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if (gaudi_queue_type[i] == QUEUE_TYPE_EXT) {
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prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
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prop->hw_queues_props[i].driver_only = 0;
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@ -370,9 +371,6 @@ static int gaudi_get_fixed_properties(struct hl_device *hdev)
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}
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}
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for (; i < HL_MAX_QUEUES; i++)
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prop->hw_queues_props[i].type = QUEUE_TYPE_NA;
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prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
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prop->sync_stream_first_sob = 0;
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prop->sync_stream_first_mon = 0;
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@ -548,7 +546,8 @@ static int gaudi_early_init(struct hl_device *hdev)
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(unsigned long long) pci_resource_len(pdev,
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SRAM_BAR_ID),
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SRAM_BAR_SIZE);
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return -ENODEV;
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rc = -ENODEV;
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goto free_queue_props;
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}
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if (pci_resource_len(pdev, CFG_BAR_ID) != CFG_BAR_SIZE) {
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@ -558,20 +557,26 @@ static int gaudi_early_init(struct hl_device *hdev)
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(unsigned long long) pci_resource_len(pdev,
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CFG_BAR_ID),
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CFG_BAR_SIZE);
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return -ENODEV;
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rc = -ENODEV;
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goto free_queue_props;
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}
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prop->dram_pci_bar_size = pci_resource_len(pdev, HBM_BAR_ID);
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rc = hl_pci_init(hdev);
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if (rc)
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return rc;
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goto free_queue_props;
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return 0;
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free_queue_props:
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kfree(hdev->asic_prop.hw_queues_props);
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return rc;
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}
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static int gaudi_early_fini(struct hl_device *hdev)
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{
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kfree(hdev->asic_prop.hw_queues_props);
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hl_pci_fini(hdev);
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return 0;
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@ -3461,7 +3466,7 @@ static int gaudi_test_queues(struct hl_device *hdev)
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{
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int i, rc, ret_val = 0;
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for (i = 0 ; i < HL_MAX_QUEUES ; i++) {
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for (i = 0 ; i < hdev->asic_prop.max_queues ; i++) {
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if (hdev->asic_prop.hw_queues_props[i].type == QUEUE_TYPE_EXT) {
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rc = gaudi_test_queue(hdev, i);
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if (rc)
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@ -337,11 +337,19 @@ static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
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static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev);
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static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
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void goya_get_fixed_properties(struct hl_device *hdev)
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int goya_get_fixed_properties(struct hl_device *hdev)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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int i;
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prop->max_queues = GOYA_QUEUE_ID_SIZE;
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prop->hw_queues_props = kcalloc(prop->max_queues,
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sizeof(struct hw_queue_properties),
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GFP_KERNEL);
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if (!prop->hw_queues_props)
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return -ENOMEM;
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for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
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prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
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prop->hw_queues_props[i].driver_only = 0;
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@ -361,9 +369,6 @@ void goya_get_fixed_properties(struct hl_device *hdev)
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prop->hw_queues_props[i].requires_kernel_cb = 0;
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}
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for (; i < HL_MAX_QUEUES; i++)
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prop->hw_queues_props[i].type = QUEUE_TYPE_NA;
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prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
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prop->dram_base_address = DRAM_PHYS_BASE;
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@ -428,6 +433,8 @@ void goya_get_fixed_properties(struct hl_device *hdev)
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CARD_NAME_MAX_LEN);
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prop->max_pending_cs = GOYA_MAX_PENDING_CS;
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return 0;
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}
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/*
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@ -540,7 +547,11 @@ static int goya_early_init(struct hl_device *hdev)
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u32 val;
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int rc;
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goya_get_fixed_properties(hdev);
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rc = goya_get_fixed_properties(hdev);
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if (rc) {
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dev_err(hdev->dev, "Failed to get fixed properties\n");
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return rc;
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}
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/* Check BAR sizes */
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if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) {
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@ -550,7 +561,8 @@ static int goya_early_init(struct hl_device *hdev)
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(unsigned long long) pci_resource_len(pdev,
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SRAM_CFG_BAR_ID),
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CFG_BAR_SIZE);
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return -ENODEV;
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rc = -ENODEV;
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goto free_queue_props;
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}
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if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) {
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@ -560,14 +572,15 @@ static int goya_early_init(struct hl_device *hdev)
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(unsigned long long) pci_resource_len(pdev,
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MSIX_BAR_ID),
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MSIX_BAR_SIZE);
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return -ENODEV;
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rc = -ENODEV;
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goto free_queue_props;
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}
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prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
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rc = hl_pci_init(hdev);
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if (rc)
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return rc;
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goto free_queue_props;
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if (!hdev->pldm) {
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val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
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@ -577,6 +590,10 @@ static int goya_early_init(struct hl_device *hdev)
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}
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return 0;
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free_queue_props:
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kfree(hdev->asic_prop.hw_queues_props);
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return rc;
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}
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/*
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@ -589,6 +606,7 @@ static int goya_early_init(struct hl_device *hdev)
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*/
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static int goya_early_fini(struct hl_device *hdev)
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{
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kfree(hdev->asic_prop.hw_queues_props);
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hl_pci_fini(hdev);
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return 0;
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@ -31,10 +31,6 @@
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*/
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#define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + 1)
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#if (NUMBER_OF_HW_QUEUES >= HL_MAX_QUEUES)
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#error "Number of H/W queues must be smaller than HL_MAX_QUEUES"
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#endif
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#if (NUMBER_OF_INTERRUPTS > GOYA_MSIX_ENTRIES)
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#error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES"
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#endif
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@ -170,7 +166,7 @@ struct goya_device {
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u8 device_cpu_mmu_mappings_done;
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};
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void goya_get_fixed_properties(struct hl_device *hdev);
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int goya_get_fixed_properties(struct hl_device *hdev);
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int goya_mmu_init(struct hl_device *hdev);
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void goya_init_dma_qmans(struct hl_device *hdev);
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void goya_init_mme_qmans(struct hl_device *hdev);
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@ -41,8 +41,6 @@
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#define HL_SIM_MAX_TIMEOUT_US 10000000 /* 10s */
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#define HL_MAX_QUEUES 128
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#define HL_IDLE_BUSY_TS_ARR_SIZE 4096
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/* Memory */
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@ -290,14 +288,15 @@ struct hl_mmu_properties {
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* @high_pll: high PLL frequency used by the device.
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* @cb_pool_cb_cnt: number of CBs in the CB pool.
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* @cb_pool_cb_size: size of each CB in the CB pool.
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* @tpc_enabled_mask: which TPCs are enabled.
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* @max_pending_cs: maximum of concurrent pending command submissions
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* @max_queues: maximum amount of queues in the system
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* @sync_stream_first_sob: first sync object available for sync stream use
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* @sync_stream_first_mon: first monitor available for sync stream use
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* @tpc_enabled_mask: which TPCs are enabled.
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* @completion_queues_count: number of completion queues.
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*/
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struct asic_fixed_properties {
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struct hw_queue_properties hw_queues_props[HL_MAX_QUEUES];
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struct hw_queue_properties *hw_queues_props;
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struct armcp_info armcp_info;
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char uboot_ver[VERSION_MAX_LEN];
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char preboot_ver[VERSION_MAX_LEN];
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@ -336,6 +335,7 @@ struct asic_fixed_properties {
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u32 cb_pool_cb_cnt;
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u32 cb_pool_cb_size;
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u32 max_pending_cs;
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u32 max_queues;
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u16 sync_stream_first_sob;
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u16 sync_stream_first_mon;
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u8 tpc_enabled_mask;
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@ -901,7 +901,7 @@ struct hl_userptr {
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* @aborted: true if CS was aborted due to some device error.
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*/
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struct hl_cs {
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u16 jobs_in_queue_cnt[HL_MAX_QUEUES];
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u16 *jobs_in_queue_cnt;
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struct hl_ctx *ctx;
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struct list_head job_list;
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spinlock_t job_lock;
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@ -46,7 +46,7 @@ void hl_int_hw_queue_update_ci(struct hl_cs *cs)
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goto out;
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q = &hdev->kernel_queues[0];
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for (i = 0 ; i < HL_MAX_QUEUES ; i++, q++) {
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for (i = 0 ; i < hdev->asic_prop.max_queues ; i++, q++) {
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if (q->queue_type == QUEUE_TYPE_INT) {
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q->ci += cs->jobs_in_queue_cnt[i];
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q->ci &= ((q->int_queue_len << 1) - 1);
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@ -509,6 +509,7 @@ int hl_hw_queue_schedule_cs(struct hl_cs *cs)
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struct hl_device *hdev = ctx->hdev;
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struct hl_cs_job *job, *tmp;
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struct hl_hw_queue *q;
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u32 max_queues;
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int rc = 0, i, cq_cnt;
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hdev->asic_funcs->hw_queues_lock(hdev);
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@ -521,8 +522,10 @@ int hl_hw_queue_schedule_cs(struct hl_cs *cs)
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goto out;
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}
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max_queues = hdev->asic_prop.max_queues;
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q = &hdev->kernel_queues[0];
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for (i = 0, cq_cnt = 0 ; i < HL_MAX_QUEUES ; i++, q++) {
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for (i = 0, cq_cnt = 0 ; i < max_queues ; i++, q++) {
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if (cs->jobs_in_queue_cnt[i]) {
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switch (q->queue_type) {
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case QUEUE_TYPE_EXT:
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@ -601,7 +604,7 @@ int hl_hw_queue_schedule_cs(struct hl_cs *cs)
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unroll_cq_resv:
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q = &hdev->kernel_queues[0];
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for (i = 0 ; (i < HL_MAX_QUEUES) && (cq_cnt > 0) ; i++, q++) {
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for (i = 0 ; (i < max_queues) && (cq_cnt > 0) ; i++, q++) {
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if ((q->queue_type == QUEUE_TYPE_EXT ||
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q->queue_type == QUEUE_TYPE_HW) &&
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cs->jobs_in_queue_cnt[i]) {
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@ -872,7 +875,7 @@ int hl_hw_queues_create(struct hl_device *hdev)
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struct hl_hw_queue *q;
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int i, rc, q_ready_cnt;
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hdev->kernel_queues = kcalloc(HL_MAX_QUEUES,
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hdev->kernel_queues = kcalloc(asic->max_queues,
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sizeof(*hdev->kernel_queues), GFP_KERNEL);
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if (!hdev->kernel_queues) {
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@ -882,7 +885,7 @@ int hl_hw_queues_create(struct hl_device *hdev)
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/* Initialize the H/W queues */
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for (i = 0, q_ready_cnt = 0, q = hdev->kernel_queues;
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i < HL_MAX_QUEUES ; i++, q_ready_cnt++, q++) {
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i < asic->max_queues ; i++, q_ready_cnt++, q++) {
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q->queue_type = asic->hw_queues_props[i].type;
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q->supports_sync_stream =
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@ -909,9 +912,10 @@ int hl_hw_queues_create(struct hl_device *hdev)
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void hl_hw_queues_destroy(struct hl_device *hdev)
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{
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struct hl_hw_queue *q;
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u32 max_queues = hdev->asic_prop.max_queues;
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int i;
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for (i = 0, q = hdev->kernel_queues ; i < HL_MAX_QUEUES ; i++, q++)
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for (i = 0, q = hdev->kernel_queues ; i < max_queues ; i++, q++)
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queue_fini(hdev, q);
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kfree(hdev->kernel_queues);
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@ -920,9 +924,10 @@ void hl_hw_queues_destroy(struct hl_device *hdev)
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void hl_hw_queue_reset(struct hl_device *hdev, bool hard_reset)
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{
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struct hl_hw_queue *q;
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u32 max_queues = hdev->asic_prop.max_queues;
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int i;
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for (i = 0, q = hdev->kernel_queues ; i < HL_MAX_QUEUES ; i++, q++) {
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for (i = 0, q = hdev->kernel_queues ; i < max_queues ; i++, q++) {
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if ((!q->valid) ||
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((!hard_reset) && (q->queue_type == QUEUE_TYPE_CPU)))
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continue;
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