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drm/amd/display: Make couple functions in DCE80 TG static

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Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland 2018-01-24 11:23:28 -05:00 committed by Alex Deucher
parent bbad2da8b1
commit 3a97f3fff1
2 changed files with 63 additions and 68 deletions
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125
drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
View File

@ -84,7 +84,7 @@ static const struct dce110_timing_generator_offsets reg_offsets[] = {
#define DCP_REG(reg) (reg + tg110->offsets.dcp)
#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
{
uint64_t pix_dur;
uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
@ -115,6 +115,68 @@ static void program_timing(struct timing_generator *tg,
dce110_tg_program_timing(tg, timing, use_vbios);
}
static void dce80_timing_generator_enable_advanced_request(
struct timing_generator *tg,
bool enable,
const struct dc_crtc_timing *timing)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
uint32_t value = dm_read_reg(tg->ctx, addr);
if (enable) {
set_reg_field_value(
value,
0,
CRTC_START_LINE_CONTROL,
CRTC_LEGACY_REQUESTOR_EN);
} else {
set_reg_field_value(
value,
1,
CRTC_START_LINE_CONTROL,
CRTC_LEGACY_REQUESTOR_EN);
}
if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
set_reg_field_value(
value,
3,
CRTC_START_LINE_CONTROL,
CRTC_ADVANCED_START_LINE_POSITION);
set_reg_field_value(
value,
0,
CRTC_START_LINE_CONTROL,
CRTC_PREFETCH_EN);
} else {
set_reg_field_value(
value,
4,
CRTC_START_LINE_CONTROL,
CRTC_ADVANCED_START_LINE_POSITION);
set_reg_field_value(
value,
1,
CRTC_START_LINE_CONTROL,
CRTC_PREFETCH_EN);
}
set_reg_field_value(
value,
1,
CRTC_START_LINE_CONTROL,
CRTC_PROGRESSIVE_START_LINE_EARLY);
set_reg_field_value(
value,
1,
CRTC_START_LINE_CONTROL,
CRTC_INTERLACE_START_LINE_EARLY);
dm_write_reg(tg->ctx, addr, value);
}
static const struct timing_generator_funcs dce80_tg_funcs = {
.validate_timing = dce110_tg_validate_timing,
.program_timing = program_timing,
@ -176,64 +238,3 @@ void dce80_timing_generator_construct(
tg110->min_h_back_porch = 4;
}
void dce80_timing_generator_enable_advanced_request(
struct timing_generator *tg,
bool enable,
const struct dc_crtc_timing *timing)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
uint32_t value = dm_read_reg(tg->ctx, addr);
if (enable) {
set_reg_field_value(
value,
0,
CRTC_START_LINE_CONTROL,
CRTC_LEGACY_REQUESTOR_EN);
} else {
set_reg_field_value(
value,
1,
CRTC_START_LINE_CONTROL,
CRTC_LEGACY_REQUESTOR_EN);
}
if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
set_reg_field_value(
value,
3,
CRTC_START_LINE_CONTROL,
CRTC_ADVANCED_START_LINE_POSITION);
set_reg_field_value(
value,
0,
CRTC_START_LINE_CONTROL,
CRTC_PREFETCH_EN);
} else {
set_reg_field_value(
value,
4,
CRTC_START_LINE_CONTROL,
CRTC_ADVANCED_START_LINE_POSITION);
set_reg_field_value(
value,
1,
CRTC_START_LINE_CONTROL,
CRTC_PREFETCH_EN);
}
set_reg_field_value(
value,
1,
CRTC_START_LINE_CONTROL,
CRTC_PROGRESSIVE_START_LINE_EARLY);
set_reg_field_value(
value,
1,
CRTC_START_LINE_CONTROL,
CRTC_INTERLACE_START_LINE_EARLY);
dm_write_reg(tg->ctx, addr, value);
}

6
drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h
View File

@ -36,10 +36,4 @@ void dce80_timing_generator_construct(
uint32_t instance,
const struct dce110_timing_generator_offsets *offsets);
/******** HW programming ************/
void dce80_timing_generator_enable_advanced_request(
struct timing_generator *tg,
bool enable,
const struct dc_crtc_timing *timing);
#endif /* __DC_TIMING_GENERATOR_DCE80_H__ */