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powerpc/mm: Make switch_mm_irqs_off() out of line
It's too big to be inline, there is no reason to keep it that way. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [mpe: Rework to incorporate the comment changes via fixes branch] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Benjamin Herrenschmidt
Michael Ellerman
parent
a619e59c07
commit
3a2df3798d
@ -77,93 +77,8 @@ extern void switch_cop(struct mm_struct *next);
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extern int use_cop(unsigned long acop, struct mm_struct *mm);
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extern void drop_cop(unsigned long acop, struct mm_struct *mm);
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#if defined(CONFIG_PPC32)
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static inline void switch_mm_pgdir(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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/* 32-bit keeps track of the current PGDIR in the thread struct */
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tsk->thread.pgdir = mm->pgd;
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}
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#elif defined(CONFIG_PPC_BOOK3E_64)
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static inline void switch_mm_pgdir(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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/* 64-bit Book3E keeps track of current PGD in the PACA */
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get_paca()->pgd = mm->pgd;
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}
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#else
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static inline void switch_mm_pgdir(struct task_struct *tsk,
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struct mm_struct *mm) { }
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#endif
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#ifdef CONFIG_PPC_BOOK3S_64
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static inline void inc_mm_active_cpus(struct mm_struct *mm)
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{
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atomic_inc(&mm->context.active_cpus);
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}
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#else
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static inline void inc_mm_active_cpus(struct mm_struct *mm) { }
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#endif
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/*
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* switch_mm is the entry point called from the architecture independent
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* code in kernel/sched/core.c
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*/
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static inline void switch_mm_irqs_off(struct mm_struct *prev,
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struct mm_struct *next,
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struct task_struct *tsk)
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{
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bool new_on_cpu = false;
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/* Mark this context has been used on the new CPU */
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if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) {
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
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inc_mm_active_cpus(next);
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/*
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* This full barrier orders the store to the cpumask above vs
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* a subsequent operation which allows this CPU to begin loading
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* translations for next.
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*
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* When using the radix MMU that operation is the load of the
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* MMU context id, which is then moved to SPRN_PID.
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*
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* For the hash MMU it is either the first load from slb_cache
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* in switch_slb(), and/or the store of paca->mm_ctx_id in
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* copy_mm_to_paca().
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*
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* On the read side the barrier is in pte_xchg(), which orders
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* the store to the PTE vs the load of mm_cpumask.
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*/
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smp_mb();
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new_on_cpu = true;
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}
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/* Some subarchs need to track the PGD elsewhere */
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switch_mm_pgdir(tsk, next);
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/* Nothing else to do if we aren't actually switching */
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if (prev == next)
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return;
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/* We must stop all altivec streams before changing the HW
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* context
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*/
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#ifdef CONFIG_ALTIVEC
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if (cpu_has_feature(CPU_FTR_ALTIVEC))
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asm volatile ("dssall");
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#endif /* CONFIG_ALTIVEC */
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if (new_on_cpu)
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radix_kvm_prefetch_workaround(next);
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/*
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* The actual HW switching method differs between the various
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* sub architectures. Out of line for now
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*/
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switch_mmu_context(prev, next, tsk);
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}
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extern void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk);
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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@ -8,7 +8,7 @@ ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
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obj-y := fault.o mem.o pgtable.o mmap.o \
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init_$(BITS).o pgtable_$(BITS).o \
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init-common.o
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init-common.o mmu_context.o
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obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o tlb_nohash.o \
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tlb_nohash_low.o
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obj-$(CONFIG_PPC_BOOK3E) += tlb_low_$(BITS)e.o
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99
arch/powerpc/mm/mmu_context.c
Normal file
99
arch/powerpc/mm/mmu_context.c
Normal file
@ -0,0 +1,99 @@
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/*
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* Common implementation of switch_mm_irqs_off
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*
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* Copyright IBM Corp. 2017
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/mm.h>
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#include <linux/cpu.h>
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#include <asm/mmu_context.h>
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#if defined(CONFIG_PPC32)
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static inline void switch_mm_pgdir(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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/* 32-bit keeps track of the current PGDIR in the thread struct */
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tsk->thread.pgdir = mm->pgd;
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}
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#elif defined(CONFIG_PPC_BOOK3E_64)
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static inline void switch_mm_pgdir(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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/* 64-bit Book3E keeps track of current PGD in the PACA */
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get_paca()->pgd = mm->pgd;
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}
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#else
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static inline void switch_mm_pgdir(struct task_struct *tsk,
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struct mm_struct *mm) { }
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#endif
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#ifdef CONFIG_PPC_BOOK3S_64
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static inline void inc_mm_active_cpus(struct mm_struct *mm)
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{
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atomic_inc(&mm->context.active_cpus);
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}
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#else
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static inline void inc_mm_active_cpus(struct mm_struct *mm) { }
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#endif
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void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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bool new_on_cpu = false;
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/* Mark this context has been used on the new CPU */
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if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) {
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
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inc_mm_active_cpus(next);
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/*
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* This full barrier orders the store to the cpumask above vs
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* a subsequent operation which allows this CPU to begin loading
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* translations for next.
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*
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* When using the radix MMU that operation is the load of the
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* MMU context id, which is then moved to SPRN_PID.
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*
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* For the hash MMU it is either the first load from slb_cache
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* in switch_slb(), and/or the store of paca->mm_ctx_id in
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* copy_mm_to_paca().
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*
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* On the read side the barrier is in pte_xchg(), which orders
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* the store to the PTE vs the load of mm_cpumask.
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*/
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smp_mb();
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new_on_cpu = true;
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}
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/* Some subarchs need to track the PGD elsewhere */
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switch_mm_pgdir(tsk, next);
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/* Nothing else to do if we aren't actually switching */
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if (prev == next)
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return;
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/*
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* We must stop all altivec streams before changing the HW
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* context
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*/
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if (cpu_has_feature(CPU_FTR_ALTIVEC))
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asm volatile ("dssall");
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if (new_on_cpu)
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radix_kvm_prefetch_workaround(next);
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/*
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* The actual HW switching method differs between the various
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* sub architectures. Out of line for now
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*/
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switch_mmu_context(prev, next, tsk);
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}
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