mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 10:16:43 +07:00
pinctrl: iproc-gpio: Fix incorrect pinconf configurations
Fix drive strength for AON/CRMU controller; fix pull-up/down setting
for CCM/CDRU controller.
Fixes: 616043d58a ("pinctrl: Rename gpio driver from cygnus to iproc")
Signed-off-by: Li Jin <li.jin@broadcom.com>
Link: https://lore.kernel.org/r/1567054348-19685-2-git-send-email-srinath.mannam@broadcom.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Li Jin
Linus Walleij
parent
1fdbc02ce1
commit
398a1f50e3
@ -54,8 +54,12 @@
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/* drive strength control for ASIU GPIO */
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#define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
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/* drive strength control for CCM/CRMU (AON) GPIO */
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#define IPROC_GPIO_DRV0_CTRL_OFFSET 0x00
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/* pinconf for CCM GPIO */
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#define IPROC_GPIO_PULL_DN_OFFSET 0x10
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#define IPROC_GPIO_PULL_UP_OFFSET 0x14
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/* pinconf for CRMU(aon) GPIO and CCM GPIO*/
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#define IPROC_GPIO_DRV_CTRL_OFFSET 0x00
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#define GPIO_BANK_SIZE 0x200
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#define NGPIOS_PER_BANK 32
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@ -76,6 +80,12 @@ enum iproc_pinconf_param {
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IPROC_PINCON_MAX,
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};
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enum iproc_pinconf_ctrl_type {
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IOCTRL_TYPE_AON = 1,
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IOCTRL_TYPE_CDRU,
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IOCTRL_TYPE_INVALID,
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};
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/*
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* Iproc GPIO core
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*
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@ -100,6 +110,7 @@ struct iproc_gpio {
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void __iomem *base;
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void __iomem *io_ctrl;
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enum iproc_pinconf_ctrl_type io_ctrl_type;
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raw_spinlock_t lock;
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@ -461,20 +472,44 @@ static const struct pinctrl_ops iproc_pctrl_ops = {
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static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
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bool disable, bool pull_up)
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{
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void __iomem *base;
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unsigned long flags;
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unsigned int shift;
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u32 val_1, val_2;
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raw_spin_lock_irqsave(&chip->lock, flags);
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if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
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base = chip->io_ctrl;
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shift = IPROC_GPIO_SHIFT(gpio);
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if (disable) {
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iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false);
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val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
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val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
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if (disable) {
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/* no pull-up or pull-down */
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val_1 &= ~BIT(shift);
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val_2 &= ~BIT(shift);
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} else if (pull_up) {
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val_1 |= BIT(shift);
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val_2 &= ~BIT(shift);
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} else {
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val_1 &= ~BIT(shift);
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val_2 |= BIT(shift);
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}
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writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
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writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
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} else {
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iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
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pull_up);
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iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true);
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if (disable) {
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iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
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false);
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} else {
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iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
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pull_up);
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iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
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true);
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}
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}
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
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return 0;
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@ -483,14 +518,35 @@ static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
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static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
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bool *disable, bool *pull_up)
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{
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void __iomem *base;
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unsigned long flags;
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unsigned int shift;
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u32 val_1, val_2;
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raw_spin_lock_irqsave(&chip->lock, flags);
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*disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
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*pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
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if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
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base = chip->io_ctrl;
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shift = IPROC_GPIO_SHIFT(gpio);
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val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
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val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
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*pull_up = val_1 ? true : false;
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*disable = (val_1 | val_2) ? false : true;
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} else {
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*disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
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*pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
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}
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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#define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \
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((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
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((type) == IOCTRL_TYPE_CDRU) ? \
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((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
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((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
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static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
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unsigned strength)
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{
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@ -505,11 +561,8 @@ static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
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if (chip->io_ctrl) {
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base = chip->io_ctrl;
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offset = IPROC_GPIO_DRV0_CTRL_OFFSET;
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} else {
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base = chip->base;
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offset = IPROC_GPIO_REG(gpio,
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IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET);
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}
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shift = IPROC_GPIO_SHIFT(gpio);
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@ -520,11 +573,11 @@ static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
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raw_spin_lock_irqsave(&chip->lock, flags);
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strength = (strength / 2) - 1;
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for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
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offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
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val = readl(base + offset);
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val &= ~BIT(shift);
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val |= ((strength >> i) & 0x1) << shift;
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writel(val, base + offset);
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offset += 4;
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}
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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@ -541,11 +594,8 @@ static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
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if (chip->io_ctrl) {
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base = chip->io_ctrl;
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offset = IPROC_GPIO_DRV0_CTRL_OFFSET;
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} else {
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base = chip->base;
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offset = IPROC_GPIO_REG(gpio,
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IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET);
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}
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shift = IPROC_GPIO_SHIFT(gpio);
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@ -553,10 +603,10 @@ static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
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raw_spin_lock_irqsave(&chip->lock, flags);
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*strength = 0;
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for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
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offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
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val = readl(base + offset) & BIT(shift);
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val >>= shift;
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*strength += (val << i);
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offset += 4;
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}
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/* convert to mA */
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@ -734,6 +784,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
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u32 ngpios, pinconf_disable_mask = 0;
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int irq, ret;
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bool no_pinconf = false;
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enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
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/* NSP does not support drive strength config */
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if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
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@ -764,8 +815,15 @@ static int iproc_gpio_probe(struct platform_device *pdev)
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dev_err(dev, "unable to map I/O memory\n");
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return PTR_ERR(chip->io_ctrl);
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}
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if (of_device_is_compatible(dev->of_node,
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"brcm,cygnus-ccm-gpio"))
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io_ctrl_type = IOCTRL_TYPE_CDRU;
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else
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io_ctrl_type = IOCTRL_TYPE_AON;
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}
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chip->io_ctrl_type = io_ctrl_type;
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if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
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dev_err(&pdev->dev, "missing ngpios DT property\n");
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return -ENODEV;
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