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ARC: boot: Support Halt-on-reset and Run-on-reset SMP booting modes
For Run-on-reset, non masters need to spin wait. For Halt-on-reset they can jump to entry point directly. Also while at it, made reset vector handler as "the" entry point for kernel including host debugger based boot (which uses the ELF header entry point) Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
parent
f33e9c434b
commit
3971cdc202
@ -194,6 +194,16 @@ config NR_CPUS
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range 2 4096
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default "4"
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config ARC_SMP_HALT_ON_RESET
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bool "Enable Halt-on-reset boot mode"
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default y if ARC_UBOOT_SUPPORT
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help
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In SMP configuration cores can be configured as Halt-on-reset
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or they could all start at same time. For Halt-on-reset, non
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masters are parked until Master kicks them so they can start of
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at designated entry point. For other case, all jump to common
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entry point and spin wait for Master's signal.
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endif #SMP
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menuconfig ARC_CACHE
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@ -24,7 +24,7 @@
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.align 4
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# Initial 16 slots are Exception Vectors
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VECTOR stext ; Restart Vector (jump to entry point)
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VECTOR res_service ; Reset Vector
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VECTOR mem_service ; Mem exception
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VECTOR instr_service ; Instrn Error
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VECTOR EV_MachineCheck ; Fatal Machine check
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@ -86,7 +86,7 @@
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*/
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; ********* Critical System Events **********************
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VECTOR res_service ; 0x0, Restart Vector (0x0)
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VECTOR res_service ; 0x0, Reset Vector (0x0)
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VECTOR mem_service ; 0x8, Mem exception (0x1)
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VECTOR instr_service ; 0x10, Instrn Error (0x2)
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@ -155,13 +155,9 @@ int2_saved_reg:
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; ---------------------------------------------
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.section .text, "ax",@progbits
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res_service: ; processor restart
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flag 0x1 ; not implemented
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nop
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nop
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reserved: ; processor restart
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rtie ; jump to processor initializations
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reserved:
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flag 1 ; Unexpected event, halt
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;##################### Interrupt Handling ##############################
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@ -50,28 +50,37 @@
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.endm
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.section .init.text, "ax",@progbits
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.type stext, @function
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.globl stext
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stext:
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;-------------------------------------------------------------------
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; Don't clobber r0-r2 yet. It might have bootloader provided info
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;-------------------------------------------------------------------
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;----------------------------------------------------------------
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; Default Reset Handler (jumped into from Reset vector)
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; - Don't clobber r0,r1,r2 as they might have u-boot provided args
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; - Platforms can override this weak version if needed
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;----------------------------------------------------------------
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WEAK(res_service)
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j stext
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END(res_service)
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;----------------------------------------------------------------
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; Kernel Entry point
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;----------------------------------------------------------------
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ENTRY(stext)
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CPU_EARLY_SETUP
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#ifdef CONFIG_SMP
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; Ensure Boot (Master) proceeds. Others wait in platform dependent way
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; IDENTITY Reg [ 3 2 1 0 ]
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; (cpu-id) ^^^ => Zero for UP ARC700
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; => #Core-ID if SMP (Master 0)
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; Note that non-boot CPUs might not land here if halt-on-reset and
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; instead breath life from @first_lines_of_secondary, but we still
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; need to make sure only boot cpu takes this path.
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GET_CPU_ID r5
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cmp r5, 0
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mov.ne r0, r5
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jne arc_platform_smp_wait_to_boot
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mov.nz r0, r5
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#ifdef CONFIG_ARC_SMP_HALT_ON_RESET
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; Non-Master can proceed as system would be booted sufficiently
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jnz first_lines_of_secondary
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#else
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; Non-Masters wait for Master to boot enough and bring them up
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jnz arc_platform_smp_wait_to_boot
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#endif
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; Master falls thru
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#endif
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; Clear BSS before updating any globals
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; XXX: use ZOL here
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mov r5, __bss_start
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@ -102,16 +111,14 @@ stext:
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GET_TSK_STACK_BASE r9, sp ; r9 = tsk, sp = stack base(output)
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j start_kernel ; "C" entry point
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END(stext)
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#ifdef CONFIG_SMP
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;----------------------------------------------------------------
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; First lines of code run by secondary before jumping to 'C'
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;----------------------------------------------------------------
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.section .text, "ax",@progbits
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.type first_lines_of_secondary, @function
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.globl first_lines_of_secondary
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first_lines_of_secondary:
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ENTRY(first_lines_of_secondary)
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CPU_EARLY_SETUP
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@ -126,5 +133,5 @@ first_lines_of_secondary:
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GET_TSK_STACK_BASE r0, sp
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j start_kernel_secondary
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END(first_lines_of_secondary)
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#endif
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@ -12,7 +12,7 @@
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#include <asm/thread_info.h>
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OUTPUT_ARCH(arc)
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ENTRY(_stext)
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ENTRY(res_service)
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#ifdef CONFIG_CPU_BIG_ENDIAN
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jiffies = jiffies_64 + 4;
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