AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-24 21:30:53 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM64: dts: meson-gx: fix UART pclk clock name

Browse Source 
The clock-names for pclk was wrongly set to "core", but the bindings
specifies "pclk".
This was not cathed until the legacy non-documented bindings were removed.

Reported-by: Andreas Färber <afaerber@suse.de>
Fixes: f72d6f6037 ("ARM64: dts: meson-gx: use stable UART bindings with correct gate clock")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Neil Armstrong 2017-12-04 10:04:53 +01:00 committed by Kevin Hilman
parent 044d71bc6c
commit 39005e562a
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View File

@ -753,12 +753,12 @@ &uart_AO_B {
&uart_B {
clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
clock-names = "xtal", "core", "baud";
clock-names = "xtal", "pclk", "baud";
};
&uart_C {
clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
clock-names = "xtal", "core", "baud";
clock-names = "xtal", "pclk", "baud";
};
&vpu {

6
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@ -688,7 +688,7 @@ &spifc {
&uart_A {
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "core", "baud";
clock-names = "xtal", "pclk", "baud";
};
&uart_AO {
@ -703,12 +703,12 @@ &uart_AO_B {
&uart_B {
clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
clock-names = "xtal", "core", "baud";
clock-names = "xtal", "pclk", "baud";
};
&uart_C {
clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
clock-names = "xtal", "core", "baud";
clock-names = "xtal", "pclk", "baud";
};
&vpu {