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drm: omapdrm: Move reg_fields to dispc_features structure
The reg_fields feature describes DISPC registers only. Move it from the omap_dss_features structure to the dispc_features structure. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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6d85d4adb6
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38dc07039c
@ -88,6 +88,8 @@ struct dispc_features {
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u16 width, u16 height, u16 out_width, u16 out_height,
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bool mem_to_mem);
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u8 num_fifos;
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const struct dss_reg_field *reg_fields;
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const unsigned int num_reg_fields;
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const enum omap_overlay_caps *overlay_caps;
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const u32 **supported_color_modes;
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unsigned int num_mgrs;
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@ -188,6 +190,17 @@ enum mgr_reg_fields {
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DISPC_MGR_FLD_NUM,
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};
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/* DISPC register field id */
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enum dispc_feat_reg_field {
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FEAT_REG_FIRHINC,
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FEAT_REG_FIRVINC,
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FEAT_REG_FIFOHIGHTHRESHOLD,
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FEAT_REG_FIFOLOWTHRESHOLD,
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FEAT_REG_FIFOSIZE,
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FEAT_REG_HORIZONTALACCU,
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FEAT_REG_VERTICALACCU,
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};
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struct dispc_reg_field {
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u16 reg;
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u8 high;
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@ -361,6 +374,16 @@ static int dispc_get_num_mgrs(void)
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return dispc.feat->num_mgrs;
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}
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static void dispc_get_reg_field(enum dispc_feat_reg_field id,
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u8 *start, u8 *end)
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{
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if (id >= dispc.feat->num_reg_fields)
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BUG();
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*start = dispc.feat->reg_fields[id].start;
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*end = dispc.feat->reg_fields[id].end;
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}
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#define SR(reg) \
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dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
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#define RR(reg) \
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@ -1252,7 +1275,7 @@ static void dispc_init_fifos(void)
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unit = dispc.feat->buffer_size_unit;
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dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
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dispc_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
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for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
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size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
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@ -1342,8 +1365,8 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low,
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low /= unit;
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high /= unit;
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dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
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dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
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dispc_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
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dispc_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
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DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
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plane,
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@ -1510,10 +1533,8 @@ static void dispc_ovl_set_fir(enum omap_plane_id plane,
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if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
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u8 hinc_start, hinc_end, vinc_start, vinc_end;
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dss_feat_get_reg_field(FEAT_REG_FIRHINC,
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&hinc_start, &hinc_end);
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dss_feat_get_reg_field(FEAT_REG_FIRVINC,
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&vinc_start, &vinc_end);
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dispc_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
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dispc_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
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val = FLD_VAL(vinc, vinc_start, vinc_end) |
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FLD_VAL(hinc, hinc_start, hinc_end);
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@ -1530,8 +1551,8 @@ static void dispc_ovl_set_vid_accu0(enum omap_plane_id plane, int haccu,
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u32 val;
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u8 hor_start, hor_end, vert_start, vert_end;
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dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
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dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
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dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
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dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
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val = FLD_VAL(vaccu, vert_start, vert_end) |
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FLD_VAL(haccu, hor_start, hor_end);
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@ -1545,8 +1566,8 @@ static void dispc_ovl_set_vid_accu1(enum omap_plane_id plane, int haccu,
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u32 val;
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u8 hor_start, hor_end, vert_start, vert_end;
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dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
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dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
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dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
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dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
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val = FLD_VAL(vaccu, vert_start, vert_end) |
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FLD_VAL(haccu, hor_start, hor_end);
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@ -3711,6 +3732,36 @@ static void _omap_dispc_initial_config(void)
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dispc_init_mflag();
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}
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static const struct dss_reg_field omap2_dispc_reg_fields[] = {
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[FEAT_REG_FIRHINC] = { 11, 0 },
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[FEAT_REG_FIRVINC] = { 27, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
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[FEAT_REG_FIFOSIZE] = { 8, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
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[FEAT_REG_VERTICALACCU] = { 25, 16 },
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};
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static const struct dss_reg_field omap3_dispc_reg_fields[] = {
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[FEAT_REG_FIRHINC] = { 12, 0 },
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[FEAT_REG_FIRVINC] = { 28, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
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[FEAT_REG_FIFOSIZE] = { 10, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
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[FEAT_REG_VERTICALACCU] = { 25, 16 },
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};
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static const struct dss_reg_field omap4_dispc_reg_fields[] = {
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[FEAT_REG_FIRHINC] = { 12, 0 },
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[FEAT_REG_FIRVINC] = { 28, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
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[FEAT_REG_FIFOSIZE] = { 15, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 10, 0 },
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[FEAT_REG_VERTICALACCU] = { 26, 16 },
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};
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static const enum omap_overlay_caps omap2_dispc_overlay_caps[] = {
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/* OMAP_DSS_GFX */
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OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
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@ -3890,6 +3941,8 @@ static const struct dispc_features omap24xx_dispc_feats = {
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.calc_scaling = dispc_ovl_calc_scaling_24xx,
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.calc_core_clk = calc_core_clk_24xx,
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.num_fifos = 3,
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.reg_fields = omap2_dispc_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap2_dispc_reg_fields),
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.overlay_caps = omap2_dispc_overlay_caps,
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.supported_color_modes = omap2_dispc_supported_color_modes,
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.num_mgrs = 2,
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@ -3917,6 +3970,8 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
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.calc_scaling = dispc_ovl_calc_scaling_34xx,
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.calc_core_clk = calc_core_clk_34xx,
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.num_fifos = 3,
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.reg_fields = omap3_dispc_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields),
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.overlay_caps = omap3430_dispc_overlay_caps,
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.supported_color_modes = omap3_dispc_supported_color_modes,
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.num_mgrs = 2,
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@ -3944,6 +3999,8 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
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.calc_scaling = dispc_ovl_calc_scaling_34xx,
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.calc_core_clk = calc_core_clk_34xx,
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.num_fifos = 3,
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.reg_fields = omap3_dispc_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields),
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.overlay_caps = omap3430_dispc_overlay_caps,
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.supported_color_modes = omap3_dispc_supported_color_modes,
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.num_mgrs = 2,
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@ -3971,6 +4028,8 @@ static const struct dispc_features omap36xx_dispc_feats = {
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.calc_scaling = dispc_ovl_calc_scaling_34xx,
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.calc_core_clk = calc_core_clk_34xx,
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.num_fifos = 3,
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.reg_fields = omap3_dispc_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields),
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.overlay_caps = omap3630_dispc_overlay_caps,
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.supported_color_modes = omap3_dispc_supported_color_modes,
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.num_mgrs = 2,
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@ -3998,6 +4057,8 @@ static const struct dispc_features am43xx_dispc_feats = {
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.calc_scaling = dispc_ovl_calc_scaling_34xx,
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.calc_core_clk = calc_core_clk_34xx,
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.num_fifos = 3,
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.reg_fields = omap3_dispc_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields),
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.overlay_caps = omap3430_dispc_overlay_caps,
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.supported_color_modes = omap3_dispc_supported_color_modes,
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.num_mgrs = 1,
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@ -4025,6 +4086,8 @@ static const struct dispc_features omap44xx_dispc_feats = {
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.calc_scaling = dispc_ovl_calc_scaling_44xx,
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.calc_core_clk = calc_core_clk_44xx,
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.num_fifos = 5,
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.reg_fields = omap4_dispc_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields),
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.overlay_caps = omap4_dispc_overlay_caps,
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.supported_color_modes = omap4_dispc_supported_color_modes,
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.num_mgrs = 3,
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@ -4057,6 +4120,8 @@ static const struct dispc_features omap54xx_dispc_feats = {
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.calc_scaling = dispc_ovl_calc_scaling_44xx,
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.calc_core_clk = calc_core_clk_44xx,
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.num_fifos = 5,
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.reg_fields = omap4_dispc_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields),
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.overlay_caps = omap4_dispc_overlay_caps,
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.supported_color_modes = omap4_dispc_supported_color_modes,
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.num_mgrs = 4,
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@ -33,9 +33,6 @@ struct dss_param_range {
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};
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struct omap_dss_features {
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const struct dss_reg_field *reg_fields;
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const int num_reg_fields;
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const enum dss_feat_id *features;
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const int num_features;
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@ -46,56 +43,6 @@ struct omap_dss_features {
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/* This struct is assigned to one of the below during initialization */
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static const struct omap_dss_features *omap_current_dss_features;
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static const struct dss_reg_field omap2_dss_reg_fields[] = {
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[FEAT_REG_FIRHINC] = { 11, 0 },
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[FEAT_REG_FIRVINC] = { 27, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
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[FEAT_REG_FIFOSIZE] = { 8, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
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[FEAT_REG_VERTICALACCU] = { 25, 16 },
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};
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static const struct dss_reg_field omap3_dss_reg_fields[] = {
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[FEAT_REG_FIRHINC] = { 12, 0 },
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[FEAT_REG_FIRVINC] = { 28, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
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[FEAT_REG_FIFOSIZE] = { 10, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
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[FEAT_REG_VERTICALACCU] = { 25, 16 },
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};
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static const struct dss_reg_field am43xx_dss_reg_fields[] = {
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[FEAT_REG_FIRHINC] = { 12, 0 },
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[FEAT_REG_FIRVINC] = { 28, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
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[FEAT_REG_FIFOSIZE] = { 10, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
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[FEAT_REG_VERTICALACCU] = { 25, 16 },
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};
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static const struct dss_reg_field omap4_dss_reg_fields[] = {
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[FEAT_REG_FIRHINC] = { 12, 0 },
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[FEAT_REG_FIRVINC] = { 28, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
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[FEAT_REG_FIFOSIZE] = { 15, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 10, 0 },
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[FEAT_REG_VERTICALACCU] = { 26, 16 },
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};
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static const struct dss_reg_field omap5_dss_reg_fields[] = {
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[FEAT_REG_FIRHINC] = { 12, 0 },
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[FEAT_REG_FIRVINC] = { 28, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
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[FEAT_REG_FIFOSIZE] = { 15, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 10, 0 },
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[FEAT_REG_VERTICALACCU] = { 26, 16 },
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};
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static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
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/* OMAP_DSS_CHANNEL_LCD */
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OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
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@ -358,9 +305,6 @@ static const enum dss_feat_id omap5_dss_feat_list[] = {
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/* OMAP2 DSS Features */
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static const struct omap_dss_features omap2_dss_features = {
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.reg_fields = omap2_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
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.features = omap2_dss_feat_list,
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.num_features = ARRAY_SIZE(omap2_dss_feat_list),
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@ -370,9 +314,6 @@ static const struct omap_dss_features omap2_dss_features = {
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/* OMAP3 DSS Features */
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static const struct omap_dss_features omap3430_dss_features = {
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.reg_fields = omap3_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
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.features = omap3430_dss_feat_list,
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.num_features = ARRAY_SIZE(omap3430_dss_feat_list),
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@ -385,9 +326,6 @@ static const struct omap_dss_features omap3430_dss_features = {
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* vdds_dsi regulator.
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*/
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static const struct omap_dss_features am35xx_dss_features = {
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.reg_fields = omap3_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
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.features = am35xx_dss_feat_list,
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.num_features = ARRAY_SIZE(am35xx_dss_feat_list),
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@ -396,9 +334,6 @@ static const struct omap_dss_features am35xx_dss_features = {
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};
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static const struct omap_dss_features am43xx_dss_features = {
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.reg_fields = am43xx_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(am43xx_dss_reg_fields),
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.features = am43xx_dss_feat_list,
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.num_features = ARRAY_SIZE(am43xx_dss_feat_list),
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@ -407,9 +342,6 @@ static const struct omap_dss_features am43xx_dss_features = {
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};
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static const struct omap_dss_features omap3630_dss_features = {
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.reg_fields = omap3_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
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.features = omap3630_dss_feat_list,
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.num_features = ARRAY_SIZE(omap3630_dss_feat_list),
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@ -420,9 +352,6 @@ static const struct omap_dss_features omap3630_dss_features = {
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/* OMAP4 DSS Features */
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/* For OMAP4430 ES 1.0 revision */
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static const struct omap_dss_features omap4430_es1_0_dss_features = {
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.reg_fields = omap4_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
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.features = omap4430_es1_0_dss_feat_list,
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.num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
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@ -432,9 +361,6 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = {
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/* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */
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static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
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.reg_fields = omap4_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
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.features = omap4430_es2_0_1_2_dss_feat_list,
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.num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
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@ -444,9 +370,6 @@ static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
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/* For all the other OMAP4 versions */
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static const struct omap_dss_features omap4_dss_features = {
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.reg_fields = omap4_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
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.features = omap4_dss_feat_list,
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.num_features = ARRAY_SIZE(omap4_dss_feat_list),
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@ -456,9 +379,6 @@ static const struct omap_dss_features omap4_dss_features = {
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/* OMAP5 DSS Features */
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static const struct omap_dss_features omap5_dss_features = {
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.reg_fields = omap5_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),
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.features = omap5_dss_feat_list,
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.num_features = ARRAY_SIZE(omap5_dss_feat_list),
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@ -497,15 +417,6 @@ bool dss_has_feature(enum dss_feat_id id)
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return false;
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}
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void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
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{
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if (id >= omap_current_dss_features->num_reg_fields)
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BUG();
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*start = omap_current_dss_features->reg_fields[id].start;
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*end = omap_current_dss_features->reg_fields[id].end;
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}
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void dss_features_init(enum omapdss_version version)
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{
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switch (version) {
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|
@ -64,17 +64,6 @@ enum dss_feat_id {
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FEAT_MFLAG,
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};
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/* DSS register field id */
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enum dss_feat_reg_field {
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FEAT_REG_FIRHINC,
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FEAT_REG_FIRVINC,
|
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FEAT_REG_FIFOHIGHTHRESHOLD,
|
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FEAT_REG_FIFOLOWTHRESHOLD,
|
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FEAT_REG_FIFOSIZE,
|
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FEAT_REG_HORIZONTALACCU,
|
||||
FEAT_REG_VERTICALACCU,
|
||||
};
|
||||
|
||||
enum dss_range_param {
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FEAT_PARAM_DSS_FCK,
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FEAT_PARAM_DSS_PCD,
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@ -89,7 +78,6 @@ unsigned long dss_feat_get_param_min(enum dss_range_param param);
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||||
unsigned long dss_feat_get_param_max(enum dss_range_param param);
|
||||
|
||||
bool dss_has_feature(enum dss_feat_id id);
|
||||
void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end);
|
||||
void dss_features_init(enum omapdss_version version);
|
||||
|
||||
enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
|
||||
|
Loading…
Reference in New Issue
Block a user