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[ARM] 3825/1: iop3xx: use cp6 enable/disable macros
Add CP6 enable/disable sequences to the timekeeping code and the IRQ code. As a result, we can't depend on CP6 access being enabled when we enter get_irqnr_and_base anymore, so switch the latter over to using memory-mapped accesses for now. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Lennert Buytenhek
Russell King
parent
0b29de4a6a
commit
38ce73ebd7
@ -27,12 +27,16 @@ static u32 iop321_mask /* = 0 */;
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static inline void intctl_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intstr_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val));
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iop3xx_cp6_disable();
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}
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static void
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@ -61,24 +65,7 @@ struct irq_chip ext_chip = {
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void __init iop321_init_irq(void)
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{
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unsigned int i, tmp;
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/* Enable access to coprocessor 6 for dealing with IRQs.
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* From RMK:
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* Basically, the Intel documentation here is poor. It appears that
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* you need to set the bit to be able to access the coprocessor from
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* SVC mode. Whether that allows access from user space or not is
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* unclear.
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*/
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asm volatile (
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"orr %0, %0, %1\n\t"
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"mcr p15, 0, %0, c15, c1, 0\n\t"
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/* The action is delayed, so we have to do this: */
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"mov %0, %0\n\t"
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"sub pc, pc, #4"
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: "=r" (tmp) : "i" (1 << 6) );
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unsigned int i;
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intctl_write(0); // disable all interrupts
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intstr_write(0); // treat all as IRQ
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@ -28,25 +28,33 @@ static u32 iop331_mask1 = 0;
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static inline void intctl_write0(u32 val)
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{
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// INTCTL0
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iop3xx_cp6_enable();
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asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intctl_write1(u32 val)
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{
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// INTCTL1
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iop3xx_cp6_enable();
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asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intstr_write0(u32 val)
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{
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// INTSTR0
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iop3xx_cp6_enable();
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asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intstr_write1(u32 val)
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{
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// INTSTR1
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iop3xx_cp6_enable();
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asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val));
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iop3xx_cp6_disable();
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}
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static void
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@ -93,24 +101,7 @@ struct irq_chip iop331_irqchip2 = {
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void __init iop331_init_irq(void)
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{
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unsigned int i, tmp;
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/* Enable access to coprocessor 6 for dealing with IRQs.
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* From RMK:
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* Basically, the Intel documentation here is poor. It appears that
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* you need to set the bit to be able to access the coprocessor from
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* SVC mode. Whether that allows access from user space or not is
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* unclear.
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*/
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asm volatile (
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"orr %0, %0, %1\n\t"
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"mcr p15, 0, %0, c15, c1, 0\n\t"
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/* The action is delayed, so we have to do this: */
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"mov %0, %0\n\t"
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"sub pc, pc, #4"
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: "=r" (tmp) : "i" (1 << 6) );
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unsigned int i;
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intctl_write0(0); // disable all interrupts
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intctl_write1(0);
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@ -51,7 +51,9 @@ iop3xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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write_seqlock(&xtime_lock);
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1));
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iop3xx_cp6_disable();
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while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1)
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>= ticks_per_jiffy) {
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@ -85,10 +87,12 @@ void __init iop3xx_init_time(unsigned long tick_rate)
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* We use timer 0 for our timer interrupt, and timer 1 as
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* monotonic counter for tracking missed jiffies.
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*/
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1));
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asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
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asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff));
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asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl));
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iop3xx_cp6_disable();
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setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq);
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}
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@ -17,7 +17,8 @@
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mov \irqnr, #0
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mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC
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ldr \base, =IOP3XX_REG_ADDR(0x07D8)
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ldr \irqstat, [\base] @ Read IINTSRC
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cmp \irqstat, #0
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beq 1001f
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clz \irqnr, \irqstat
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@ -17,10 +17,11 @@
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mov \irqnr, #0
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mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0
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ldr \base, =IOP3XX_REG_ADDR(0x7A0)
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ldr \irqstat, [\base] @ Read IINTSRC0
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cmp \irqstat, #0
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bne 1002f
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mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1
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ldr \irqstat, [\base, #4] @ Read IINTSRC1
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cmp \irqstat, #0
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beq 1001f
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clz \irqnr, \irqstat
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