From d6e5a4f84e2882f95b088c20995aba73e90e35fd Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Wed, 12 Dec 2018 15:47:54 +0530 Subject: [PATCH 01/38] dt-bindings: iio: adc: Add binding for ADC on pms405 PMIC PMS405 contains a variant of the spmi-adc-rev2 ADC. Create a new compatible inorder to handle any differences. Reviewed-by: Rob Herring Signed-off-by: Amit Kucheria Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt index c81993f8d8c3..c8787688122a 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt @@ -13,6 +13,7 @@ VADC node: Definition: Should contain "qcom,spmi-vadc". Should contain "qcom,spmi-adc5" for PMIC5 ADC driver. Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver. + Should contain "qcom,pms405-adc" for PMS405 PMIC - reg: Usage: required From f95f57e4372207ede83ac28f300aba719b271ed5 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 13 Dec 2018 10:32:00 -0800 Subject: [PATCH 02/38] arm64: dts: qcom: qcs404: Fix regulator supply names The regulator definition got their supply names cleaned up during upstreaming, so they no longer match the driver defined names. Update the supply names. Also fill out the missing voltage of SMPS 5. Fixes: 0b363f5b871c ("arm64: dts: qcom: qcs404: Add PMS405 RPM regulators") Reported-by: Nicolas Dechesne Reviewed-by: Niklas Cassel Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 28 ++++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 50b3589c7f15..536f735243d2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -37,18 +37,18 @@ &rpm_requests { pms405-regulators { compatible = "qcom,rpm-pms405-regulators"; - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-l1-l2-supply = <&vreg_s5_1p35>; - vdd-l3-l8-supply = <&vreg_s5_1p35>; - vdd-l4-supply = <&vreg_s5_1p35>; - vdd-l5-l6-supply = <&vreg_s4_1p8>; - vdd-l7-supply = <&vph_pwr>; - vdd-l9-supply = <&vreg_s5_1p35>; - vdd-l10-l11-l12-l13-supply = <&vph_pwr>; + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_l1_l2-supply = <&vreg_s5_1p35>; + vdd_l3_l8-supply = <&vreg_s5_1p35>; + vdd_l4-supply = <&vreg_s5_1p35>; + vdd_l5_l6-supply = <&vreg_s4_1p8>; + vdd_l7-supply = <&vph_pwr>; + vdd_l9-supply = <&vreg_s5_1p35>; + vdd_l10_l11_l12_l13-supply = <&vph_pwr>; vreg_s4_1p8: s4 { regulator-min-microvolt = <1728000>; @@ -56,8 +56,8 @@ vreg_s4_1p8: s4 { }; vreg_s5_1p35: s5 { - regulator-min-microvolt = <>; - regulator-max-microvolt = <>; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; }; vreg_l1_1p3: l1 { From 71f1fdd9c300a92027126dfab5db7125dc4e283d Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Mon, 11 Mar 2019 16:06:02 +0200 Subject: [PATCH 03/38] arm64: dts: sdm845: Include the interconnect resources DT header Include the device tree header for the on-chip interconnect endpoint resources on sdm845 devices. This will allow using the "interconnects" property in DT nodes to describe the interconnect path resources they use. The sdm845 interconnect provider DT node is already present, but the header file with the resources is not included, so let's fix this. Reviewed-by: Evan Green Signed-off-by: Georgi Djakov Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5308f1671824..be4d4c5859c0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include From 4dfa70ea0f74bd4fd819292fe950f734ffe47c86 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Sun, 24 Mar 2019 22:02:04 +0530 Subject: [PATCH 04/38] arm64: dts: qcom: qcs404: Add Ethernet node Add the ethernet node found in QCS404 platform. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index e8fd26633d57..32f2f51bbf7f 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -479,6 +479,27 @@ blsp1_uart2: serial@78b1000 { status = "okay"; }; + ethernet: ethernet@7a80000 { + compatible = "qcom,qcs404-ethqos"; + reg = <0x07a80000 0x10000>, + <0x07a96000 0x100>; + reg-names = "stmmaceth", "rgmii"; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + clocks = <&gcc GCC_ETH_AXI_CLK>, + <&gcc GCC_ETH_SLAVE_AHB_CLK>, + <&gcc GCC_ETH_PTP_CLK>, + <&gcc GCC_ETH_RGMII_CLK>; + interrupts = , + ; + interrupt-names = "macirq", "eth_lpi"; + + snps,tso; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + + status = "disabled"; + }; + wifi: wifi@a000000 { compatible = "qcom,wcn3990-wifi"; reg = <0xa000000 0x800000>; From 0253735f503ac502fa775e96375d2f6c192bfe07 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Sun, 24 Mar 2019 22:02:05 +0530 Subject: [PATCH 05/38] arm64: dts: qcom: qcs404: Enable ethernet for EVB-4000 EVB-4000 comes with ethernet so enable it and add pinctrl bindings. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts | 82 ++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts index 11269ad3de0d..8234cff414de 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts +++ b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts @@ -3,9 +3,91 @@ /dts-v1/; +#include #include "qcs404-evb.dtsi" / { model = "Qualcomm Technologies, Inc. QCS404 EVB 4000"; compatible = "qcom,qcs404-evb"; }; + +ðernet { + status = "ok"; + + snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 10000>; + + pinctrl-names = "default"; + pinctrl-0 = <ðernet_defaults>; + + phy-handle = <&phy1>; + phy-mode = "rgmii"; + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "snps,dwmac-mdio"; + phy1: phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + device_type = "ethernet-phy"; + reg = <0x4>; + }; + }; +}; + +&tlmm { + ethernet_defaults: ethernet-defaults { + int { + pins = "gpio61"; + function = "rgmii_int"; + bias-disable; + drive-strength = <2>; + }; + mdc { + pins = "gpio76"; + function = "rgmii_mdc"; + bias-pull-up; + }; + mdio { + pins = "gpio75"; + function = "rgmii_mdio"; + bias-pull-up; + }; + tx { + pins = "gpio67", "gpio66", "gpio65", "gpio64"; + function = "rgmii_tx"; + bias-pull-up; + drive-strength = <16>; + }; + rx { + pins = "gpio73", "gpio72", "gpio71", "gpio70"; + function = "rgmii_rx"; + bias-disable; + drive-strength = <2>; + }; + tx-ctl { + pins = "gpio68"; + function = "rgmii_ctl"; + bias-pull-up; + drive-strength = <16>; + }; + rx-ctl { + pins = "gpio74"; + function = "rgmii_ctl"; + bias-disable; + drive-strength = <2>; + }; + tx-ck { + pins = "gpio63"; + function = "rgmii_ck"; + bias-pull-up; + drive-strength = <16>; + }; + rx-ck { + pins = "gpio69"; + function = "rgmii_ck"; + bias-disable; + drive-strength = <2>; + }; + }; +}; From 331ab98f8c4a38b804ec65bd99fbef07614950a3 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sun, 24 Mar 2019 22:02:06 +0530 Subject: [PATCH 06/38] arm64: dts: qcom: qcs404: Fix voltages l3 PMS405 L3 is outside the acceptable range, causing PCIe to fail. Fix these. Signed-off-by: Bjorn Andersson Signed-off-by: Khasim Syed Mohammed Signed-off-by: Vinod Koul [bjorn: Hunk fixing up S5 already applied, updated commit message] Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 536f735243d2..bdb26a5b103d 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -71,7 +71,7 @@ vreg_l2_1p275: l2 { }; vreg_l3_1p05: l3 { - regulator-min-microvolt = <976000>; + regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1160000>; }; From 6703a27327ddc7375c922ffeeffcc48a6bc98720 Mon Sep 17 00:00:00 2001 From: Khasim Syed Mohammed Date: Sun, 24 Mar 2019 22:02:09 +0530 Subject: [PATCH 07/38] arm64: dts: qcom: qcs404: Remove default setting of controlled-remotely for BAM DMA The property controlled-remotely should not be set by default for qcs-404 device, it should be set based on the secure boot options (TZ or ATF) preferred by the platform. Hence, the controlled-remotely property is moved to platform specific dts files. Signed-off-by: Khasim Syed Mohammed Signed-off-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 -- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index bdb26a5b103d..985f6004b729 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -21,6 +21,14 @@ vph_pwr: vph-pwr-regulator { }; }; +&blsp1_dma { + qcom,controlled-remotely; +}; + +&blsp2_dma { + qcom,controlled-remotely; +}; + &remoteproc_adsp { status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 32f2f51bbf7f..ffedf9640af7 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -435,7 +435,6 @@ blsp1_dma: dma@7884000 { clocks = <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; - qcom,controlled-remotely = <1>; qcom,ee = <0>; status = "okay"; }; @@ -680,7 +679,6 @@ blsp2_dma: dma@7ac4000 { clocks = <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; - qcom,controlled-remotely = <1>; qcom,ee = <0>; status = "disabled"; }; From cb79a81fd98fc485a9d0506391ad197791ba023f Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Mon, 25 Feb 2019 13:17:02 +0100 Subject: [PATCH 08/38] dt-bindings: ufs: Add msm8998 compatible string Add "qcom,msm8998-ufshc" compatible string. Tested-by: Lee Jones Signed-off-by: Marc Gonzalez Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index 5111e9130bc3..991e21ee7b44 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -11,6 +11,7 @@ Required properties: the appropriate jedec string: "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0" "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0" + "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0" "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0" - interrupts : - reg : From 695942de1da7a095f1dc8742fc94acf864eb4f18 Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Mon, 25 Feb 2019 13:17:44 +0100 Subject: [PATCH 09/38] arm64: dts: qcom: msm8998: Allow UFSHC driver to set-load The UFS host controller driver needs to set the load on 3 power rails (l20, l26, s4) but the operation fails silently unless we specify the regulator-allow-set-load property in the corresponding DT nodes. Tested-by: Lee Jones Reviewed-by: Jeffrey Hugo Signed-off-by: Marc Gonzalez Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi index f0901067b043..19775cae1381 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi @@ -111,6 +111,7 @@ vreg_s3a_1p35: s3 { vreg_s4a_1p8: s4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-allow-set-load; }; vreg_s5a_2p04: s5 { regulator-min-microvolt = <1904000>; @@ -195,6 +196,7 @@ vreg_l19a_3p0: l19 { vreg_l20a_2p95: l20 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; + regulator-allow-set-load; }; vreg_l21a_2p95: l21 { regulator-min-microvolt = <2960000>; @@ -221,6 +223,7 @@ vreg_l25a_3p3: l25 { vreg_l26a_1p2: l26 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-allow-set-load; }; vreg_l28_3p0: l28 { regulator-min-microvolt = <3008000>; From cd3dbe2a4e6cedec80e6d1f07aea8bcbef365170 Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Mon, 25 Feb 2019 13:18:43 +0100 Subject: [PATCH 10/38] arm64: dts: qcom: msm8998: Add UFS nodes Add host controller and PHY DT nodes. Tested-by: Lee Jones Signed-off-by: Marc Gonzalez Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 19 +++++++ arch/arm64/boot/dts/qcom/msm8998.dtsi | 65 +++++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi index 19775cae1381..6329ba4777cc 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi @@ -270,6 +270,25 @@ &sdhc2 { pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; }; +&ufshc { + vcc-supply = <&vreg_l20a_2p95>; + vccq-supply = <&vreg_l26a_1p2>; + vccq2-supply = <&vreg_s4a_1p8>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; +}; + +&ufsphy { + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + vddp-ref-clk-supply = <&vreg_l26a_1p2>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; +}; + &usb3 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 3fd0769fe648..3d0aeb3211de 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -983,6 +983,71 @@ intc: interrupt-controller@17a00000 { redistributor-stride = <0x0 0x20000>; interrupts = ; }; + + ufshc: ufshc@1da4000 { + compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x01da4000 0x2500>; + interrupts = ; + phys = <&ufsphy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + power-domains = <&gcc UFS_GDSC>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_AXI_CLK>, + <&gcc GCC_AGGRE1_UFS_AXI_CLK>, + <&gcc GCC_UFS_AHB_CLK>, + <&gcc GCC_UFS_UNIPRO_CORE_CLK>, + <&rpmcc RPM_SMD_LN_BB_CLK1>, + <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + resets = <&gcc GCC_UFS_BCR>; + reset-names = "rst"; + }; + + ufsphy: phy@1da7000 { + compatible = "qcom,msm8998-qmp-ufs-phy"; + reg = <0x01da7000 0x18c>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clock-names = + "ref", + "ref_aux"; + clocks = + <&gcc GCC_UFS_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_AUX_CLK>; + + ufsphy_lanes: lanes@1da7400 { + reg = <0x01da7400 0x128>, + <0x01da7600 0x1fc>, + <0x01da7c00 0x1dc>, + <0x01da7800 0x128>, + <0x01da7a00 0x1fc>; + #phy-cells = <0>; + }; + }; }; }; From a60a072c5e7fa49ca3ae5bb45b6038fd05b84295 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Tue, 26 Mar 2019 22:29:33 +0530 Subject: [PATCH 11/38] arm64: dts: qcom: pms405: add spmi regulators The PMS405 sports 5 SMPS and 13 LDO regulators, add the regulators to pms405 DTS. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Khasim Syed Mohammed Signed-off-by: Vinod Koul [bjorn: updated label] Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pms405.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 1bb836d1e8aa..e8e186bc1ea7 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -131,4 +131,15 @@ rtc@6000 { interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; }; + + pms405_1: pms405@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pms405_spmi_regulators: regulators { + compatible = "qcom,pms405-regulators"; + }; + }; }; From 8faea8edbb35c09d1c3b23d7e8f1459cea40ab6b Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Tue, 26 Mar 2019 22:29:34 +0530 Subject: [PATCH 12/38] arm64: dts: qcom: qcs404-evb: add spmi regulators Define the EVB pms405_s3 supplies. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Khasim Syed Mohammed Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 985f6004b729..62c47ca31c9d 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -29,6 +29,18 @@ &blsp2_dma { qcom,controlled-remotely; }; +&pms405_spmi_regulators { + vdd_s3-supply = <&pms405_s3>; + + pms405_s3: s3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd_apc"; + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1352000>; + }; +}; + &remoteproc_adsp { status = "ok"; }; From 60f77ae7d1c1ffbc5af34c5b1a7f3f7ecc52637c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 4 Mar 2019 23:08:23 -0800 Subject: [PATCH 13/38] arm64: dts: qcom: qcs404-evb: Enable uart3 and add Bluetooth Enable blsp1_uart3, define its pinconf and add the bluetooth node. It seems provisioning is lacking a valid BD address, preventing the interface from initializing, so provide a dummy for now. Tested-by: Vinod Koul Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 45 ++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 62c47ca31c9d..2c3127167e3c 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -7,6 +7,7 @@ / { aliases { serial0 = &blsp1_uart2; + serial1 = &blsp1_uart3; }; chosen { @@ -19,6 +20,32 @@ vph_pwr: vph-pwr-regulator { regulator-always-on; regulator-boot-on; }; + + vdd_ch0_3p3: + vdd_esmps3_3p3: vdd-esmps3-3p3-regulator { + compatible = "regulator-fixed"; + regulator-name = "eSMPS3_3P3"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&blsp1_uart3 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + vddio-supply = <&vreg_l6_1p8>; + vddxo-supply = <&vreg_l5_1p8>; + vddrf-supply = <&vreg_l1_1p3>; + vddch0-supply = <&vdd_ch0_3p3>; + + local-bd-address = [ 02 00 00 00 5a ad ]; + + max-speed = <3200000>; + }; }; &blsp1_dma { @@ -225,3 +252,21 @@ tx { bias-disable; }; }; + +&blsp1_uart3_default { + cts { + pins = "gpio84"; + bias-disable; + }; + + rts-tx { + pins = "gpio85", "gpio82"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio83"; + bias-pull-up; + }; +}; From 596a434369f6ed9339c398d36b44a680ad317de6 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 20 Mar 2019 13:39:45 +0530 Subject: [PATCH 14/38] arm64: dts: sdm845: Include rpmpd DT header In order to fix dependencies with rpmpd DT entries, the header was dropped and hardcoded values were added for opp-level, during the previous merge window. Add the header back in now and remove the hardcodings, effectively reverting commit '08585d21de9875a6064b350957faa0460a4c69a6: arm64: dts: sdm845: Fixup dependency on RPMPD includes' Signed-off-by: Rajendra Nayak Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index be4d4c5859c0..9f70b47a3dec 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -2099,43 +2100,43 @@ rpmhpd_opp_table: opp-table { compatible = "operating-points-v2"; rpmhpd_opp_ret: opp1 { - opp-level = <16>; + opp-level = ; }; rpmhpd_opp_min_svs: opp2 { - opp-level = <48>; + opp-level = ; }; rpmhpd_opp_low_svs: opp3 { - opp-level = <64>; + opp-level = ; }; rpmhpd_opp_svs: opp4 { - opp-level = <128>; + opp-level = ; }; rpmhpd_opp_svs_l1: opp5 { - opp-level = <192>; + opp-level = ; }; rpmhpd_opp_nom: opp6 { - opp-level = <256>; + opp-level = ; }; rpmhpd_opp_nom_l1: opp7 { - opp-level = <320>; + opp-level = ; }; rpmhpd_opp_nom_l2: opp8 { - opp-level = <336>; + opp-level = ; }; rpmhpd_opp_turbo: opp9 { - opp-level = <384>; + opp-level = ; }; rpmhpd_opp_turbo_l1: opp10 { - opp-level = <416>; + opp-level = ; }; }; }; From 503250482c9c7759ee7c5bdc5d4f5e703cb1b417 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:07 +0530 Subject: [PATCH 15/38] arm64: dts: msm8998: thermal: split address space into two We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for msm8998 that has a similar register layout. The order is important (TM before SROT) because we make an assumption that SROT is always the second address space in order to support legacy DTs. Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 3fd0769fe648..ac25e9142cbd 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -590,17 +590,19 @@ spmi_bus: spmi@800f000 { cell-index = <0>; }; - tsens0: thermal@10aa000 { + tsens0: thermal@10ab000 { compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; - reg = <0x10aa000 0x2000>; + reg = <0x10ab000 0x1000>, /* TM */ + <0x10aa000 0x1000>; /* SROT */ #qcom,sensors = <12>; #thermal-sensor-cells = <1>; }; - tsens1: thermal@10ad000 { + tsens1: thermal@10ae000 { compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; - reg = <0x10ad000 0x2000>; + reg = <0x10ae000 0x1000>, /* TM */ + <0x10ad000 0x1000>; /* SROT */ #qcom,sensors = <8>; #thermal-sensor-cells = <1>; From 86f93c93dd5005f0aeb8ce84c2113e21a6006c7d Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:08 +0530 Subject: [PATCH 16/38] arm64: dts: msm8998: efficiency is not valid property efficiency comes from downstream. The valid upstream property is capacity-dmips-mhz but until we can come up with those numbers, remove this property. Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index ac25e9142cbd..0b6de0c29ee8 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -78,7 +78,6 @@ CPU0: cpu@0 { compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; - efficiency = <1024>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -97,7 +96,6 @@ CPU1: cpu@1 { compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; - efficiency = <1024>; next-level-cache = <&L2_0>; L1_I_1: l1-icache { compatible = "arm,arch-cache"; @@ -112,7 +110,6 @@ CPU2: cpu@2 { compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; - efficiency = <1024>; next-level-cache = <&L2_0>; L1_I_2: l1-icache { compatible = "arm,arch-cache"; @@ -127,7 +124,6 @@ CPU3: cpu@3 { compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; - efficiency = <1024>; next-level-cache = <&L2_0>; L1_I_3: l1-icache { compatible = "arm,arch-cache"; @@ -142,7 +138,6 @@ CPU4: cpu@100 { compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; - efficiency = <1536>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -161,7 +156,6 @@ CPU5: cpu@101 { compatible = "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; - efficiency = <1536>; next-level-cache = <&L2_1>; L1_I_101: l1-icache { compatible = "arm,arch-cache"; @@ -176,7 +170,6 @@ CPU6: cpu@102 { compatible = "arm,armv8"; reg = <0x0 0x102>; enable-method = "psci"; - efficiency = <1536>; next-level-cache = <&L2_1>; L1_I_102: l1-icache { compatible = "arm,arch-cache"; @@ -191,7 +184,6 @@ CPU7: cpu@103 { compatible = "arm,armv8"; reg = <0x0 0x103>; enable-method = "psci"; - efficiency = <1536>; next-level-cache = <&L2_1>; L1_I_103: l1-icache { compatible = "arm,arch-cache"; From f2e8b07c1b7265bd862d00a2fbb1e8b729f9eb16 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:09 +0530 Subject: [PATCH 17/38] arm64: dts: msm8916: thermal: Add sensor for modem On platforms that have a modem, sensor 0 monitors the modem. Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0803ca8c02da..c8aa9a0986d2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -278,7 +278,21 @@ cam_crit: trip1 { type = "critical"; }; }; + }; + modem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 0>; + + trips { + modem_alert0: trip-point@0 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + }; }; }; From 0f5f91f01cad1c8ab2ba81e4c6c805608bab3cd5 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:10 +0530 Subject: [PATCH 18/38] arm64: dts: msm8996: thermal: Add temperature sensors near major peripherals msm8996 has a total of 21 temperature sensors. Populate DT with information about them. There are 2 sensors on each of the cpus - one on the top, the other below (we only expose one on the top in DT for now). For the GPU, we expose both, the one on the top and the one below. Depending on the version of the silicon, sensor 2 is either placed near the L3 cache or the venus video decoder. It would've been nice to be able to be version-specific but we don't have DTs that differentiate the two versions of silicon yet. Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 150 ++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c761269caf80..e2408ee91184 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -237,6 +237,156 @@ cpu_crit3: trip1 { }; }; }; + + gpu-thermal-top { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 6>; + + trips { + gpu1_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + gpu-thermal-bottom { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 7>; + + trips { + gpu2_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + m4m-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 1>; + + trips { + m4m_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + l3-or-venus-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 2>; + + trips { + l3_or_venus_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster0-l2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 7>; + + trips { + cluster0_l2_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster1-l2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 12>; + + trips { + cluster1_l2_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 1>; + + trips { + camera_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-dsp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 2>; + + trips { + q6_dsp_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 3>; + + trips { + mem_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modemtx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 4>; + + trips { + modemtx_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; }; timer { From b67d9c5d6f4ae0bf745d380654ca4a18706c3103 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:11 +0530 Subject: [PATCH 19/38] arm64: dts: msm8998: thermal: Fix the cpu sensor numbers The silver cluster (typically cpu0-3) are monitored by sensor IDs 1-3 on tsens controller 0. The gold cluster (typically cpu4-7) are monitored by sensor IDs 7-10 on tsens controller 0. Fixes: 4449b6f248d9a1 ("arm64: dts: qcom: msm8998: Add tsens and thermal-zones") Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 0b6de0c29ee8..108a5aa146a2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -342,7 +342,7 @@ cpu-thermal0 { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens0 6>; + thermal-sensors = <&tsens0 1>; trips { cpu_alert0: trip0 { @@ -363,7 +363,7 @@ cpu-thermal1 { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens0 7>; + thermal-sensors = <&tsens0 2>; trips { cpu_alert1: trip0 { @@ -384,7 +384,7 @@ cpu-thermal2 { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens0 8>; + thermal-sensors = <&tsens0 3>; trips { cpu_alert2: trip0 { @@ -405,7 +405,7 @@ cpu-thermal3 { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens0 9>; + thermal-sensors = <&tsens0 4>; trips { cpu_alert3: trip0 { @@ -426,7 +426,7 @@ cpu-thermal4 { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens0 10>; + thermal-sensors = <&tsens0 7>; trips { cpu_alert4: trip0 { @@ -447,7 +447,7 @@ cpu-thermal5 { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens0 11>; + thermal-sensors = <&tsens0 8>; trips { cpu_alert5: trip0 { @@ -468,7 +468,7 @@ cpu-thermal6 { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens1 0>; + thermal-sensors = <&tsens0 9>; trips { cpu_alert6: trip0 { @@ -489,7 +489,7 @@ cpu-thermal7 { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens1 1>; + thermal-sensors = <&tsens0 10>; trips { cpu_alert7: trip0 { From 9284aa44a5145a5304c82aca978df2e266524e7d Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:12 +0530 Subject: [PATCH 20/38] arm64: dts: msm8998: thermal: Fix the gpu sensor number The GPU sensor is sensor ID 13 on controller 0 Fixes: 4449b6f248d9a1 ("arm64: dts: qcom: msm8998: Add tsens and thermal-zones") Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 108a5aa146a2..56ca9ecdb0bf 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -510,7 +510,7 @@ gpu-thermal { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens1 3>; + thermal-sensors = <&tsens0 13>; }; }; From 2fa2d301cbca51263e615cd07d4140b15047cae0 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:13 +0530 Subject: [PATCH 21/38] arm64: dts: msm8998: thermal: GPU has two sensors, add the second The first sensor is on top and the second sensor below the GPU Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 56ca9ecdb0bf..b368da235663 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -506,11 +506,34 @@ cpu_crit7: trip1 { }; }; - gpu-thermal { + gpu-thermal-bottom { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 12>; + + trips { + gpu1_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + gpu-thermal-top { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 13>; + + trips { + gpu2_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; }; }; From e9d2729dec4b9052528f4c7609d0c5b4cbdf8138 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:14 +0530 Subject: [PATCH 22/38] arm64: dts: msm8998: thermal: Add temperature sensors near major peripherals msm8998 has a total of 22 temperature sensors. Populate DT with information about them. Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 135 ++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index b368da235663..26e476078cb6 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -535,6 +535,141 @@ gpu2_alert0: trip-point@0 { }; }; }; + + cluster0-mhm-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cluster0_mhm_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster1-mhm-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 6>; + + trips { + cluster1_mhm_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster1-l2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 11>; + + trips { + cluster1_l2_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 1>; + + trips { + modem_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 2>; + + trips { + mem_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 3>; + + trips { + wlan_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-dsp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 4>; + + trips { + q6_dsp_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 5>; + + trips { + camera_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + multimedia-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 6>; + + trips { + multimedia_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; }; timer { From 1c403ec27c1f597661ea787510200ed897a119b4 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:15 +0530 Subject: [PATCH 23/38] arm64: dts: sdm845: thermal: Add temperature sensors near major peripherals sdm845 has a total of 21 temperature sensors. Populate DT with information about them. Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 205 +++++++++++++++++++++++++++ 1 file changed, 205 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5308f1671824..7c0643ccef18 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2611,5 +2611,210 @@ map1 { }; }; }; + + aoss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 0>; + + trips { + aoss0_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cluster0_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cluster0_crit: cluster0_crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cluster1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 6>; + + trips { + cluster1_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cluster1_crit: cluster1_crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal-top { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 11>; + + trips { + gpu1_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + gpu-thermal-bottom { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 12>; + + trips { + gpu2_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 0>; + + trips { + aoss1_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-modem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 1>; + + trips { + q6_modem_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 2>; + + trips { + mem_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 3>; + + trips { + wlan_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 4>; + + trips { + q6_hvx_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 5>; + + trips { + camera_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 6>; + + trips { + video_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 7>; + + trips { + modem_alert0: trip-point@0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; }; }; From ae8876ddb826cc4996199163246e8699a165ca9d Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:16 +0530 Subject: [PATCH 24/38] arm64: dts: msm8998: thermal: Make trip names consistent Maintain naming consistency with what was landed for sdm845. Simplifies parsing for test tools. Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 48 +++++++++++++-------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 26e476078cb6..998017d4d847 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -338,20 +338,20 @@ slpi_smp2p_in: slave-kernel { }; thermal-zones { - cpu-thermal0 { + cpu0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 1>; trips { - cpu_alert0: trip0 { + cpu0_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit0: trip1 { + cpu0_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -359,20 +359,20 @@ cpu_crit0: trip1 { }; }; - cpu-thermal1 { + cpu1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 2>; trips { - cpu_alert1: trip0 { + cpu1_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit1: trip1 { + cpu1_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -380,20 +380,20 @@ cpu_crit1: trip1 { }; }; - cpu-thermal2 { + cpu2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 3>; trips { - cpu_alert2: trip0 { + cpu2_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit2: trip1 { + cpu2_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -401,20 +401,20 @@ cpu_crit2: trip1 { }; }; - cpu-thermal3 { + cpu3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 4>; trips { - cpu_alert3: trip0 { + cpu3_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit3: trip1 { + cpu3_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -422,20 +422,20 @@ cpu_crit3: trip1 { }; }; - cpu-thermal4 { + cpu4-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 7>; trips { - cpu_alert4: trip0 { + cpu4_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit4: trip1 { + cpu4_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -443,20 +443,20 @@ cpu_crit4: trip1 { }; }; - cpu-thermal5 { + cpu5-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 8>; trips { - cpu_alert5: trip0 { + cpu5_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit5: trip1 { + cpu5_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -464,20 +464,20 @@ cpu_crit5: trip1 { }; }; - cpu-thermal6 { + cpu6-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 9>; trips { - cpu_alert6: trip0 { + cpu6_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit6: trip1 { + cpu6_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -485,20 +485,20 @@ cpu_crit6: trip1 { }; }; - cpu-thermal7 { + cpu7-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 10>; trips { - cpu_alert7: trip0 { + cpu7_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit7: trip1 { + cpu7_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; From 032d7c6ee21b0b7e8470cbd0da6df2465c4d83b1 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:17 +0530 Subject: [PATCH 25/38] arm64: dts: msm8916: thermal: Make trip names consistent Maintain naming consistency with what was landed for sdm845. Simplifies parsing for test tools. Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c8aa9a0986d2..ea734b98ec96 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -180,19 +180,19 @@ pmu { }; thermal-zones { - cpu-thermal0 { + cpu0_1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 4>; trips { - cpu_alert0: trip0 { + cpu0_1_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit0: trip1 { + cpu0_1_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -201,7 +201,7 @@ cpu_crit0: trip1 { cooling-maps { map0 { - trip = <&cpu_alert0>; + trip = <&cpu0_1_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -210,19 +210,19 @@ map0 { }; }; - cpu-thermal1 { + cpu2_3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 3>; trips { - cpu_alert1: trip0 { + cpu2_3_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit1: trip1 { + cpu2_3_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -231,7 +231,7 @@ cpu_crit1: trip1 { cooling-maps { map0 { - trip = <&cpu_alert1>; + trip = <&cpu2_3_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -247,12 +247,12 @@ gpu-thermal { thermal-sensors = <&tsens 2>; trips { - gpu_alert: trip0 { + gpu_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - gpu_crit: trip1 { + gpu_crit: gpu_crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; @@ -267,12 +267,12 @@ camera-thermal { thermal-sensors = <&tsens 1>; trips { - cam_alert: trip0 { + cam_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cam_crit: trip1 { + cam_crit: cam_crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; From bc3ac5d25195fb8e91aa5d6b310ee035aba889f3 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:18 +0530 Subject: [PATCH 26/38] arm64: dts: msm8996: thermal: Make trip names consistent Maintain naming consistency with what was landed for sdm845. Simplifies parsing for test tools. Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index e2408ee91184..edcddc74a4fc 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -154,20 +154,20 @@ core1 { }; thermal-zones { - cpu-thermal0 { + cpu0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 3>; trips { - cpu_alert0: trip0 { + cpu0_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit0: trip1 { + cpu0_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -175,20 +175,20 @@ cpu_crit0: trip1 { }; }; - cpu-thermal1 { + cpu1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 5>; trips { - cpu_alert1: trip0 { + cpu1_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit1: trip1 { + cpu1_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -196,20 +196,20 @@ cpu_crit1: trip1 { }; }; - cpu-thermal2 { + cpu2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 8>; trips { - cpu_alert2: trip0 { + cpu2_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit2: trip1 { + cpu2_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -217,20 +217,20 @@ cpu_crit2: trip1 { }; }; - cpu-thermal3 { + cpu3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 10>; trips { - cpu_alert3: trip0 { + cpu3_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit3: trip1 { + cpu3_crit: cpu_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; From 10518bb1594066f7e894832e3cec9306e2d90f22 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 29 Mar 2019 15:42:19 +0530 Subject: [PATCH 27/38] arm64: dts: msm8916: thermal: Convert camera trip type to hot We don't have any cooling-devices related to the camera. Use the "hot" trip type so allow the temperature to be exported to userspace and remove the "critical" trip. Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index ea734b98ec96..e4b1010f70b6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -270,12 +270,7 @@ trips { cam_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; - type = "passive"; - }; - cam_crit: cam_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; + type = "hot"; }; }; }; From c35b67d3956fa54bb785376d08410d411e3052d4 Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Mon, 1 Apr 2019 16:38:37 +0200 Subject: [PATCH 28/38] arm64: dts: msm8998: Add UFS phy reset Fixup MSM8998 UFS DT nodes now that Evan's reset series has landed. https://lore.kernel.org/lkml/20190321171800.104681-1-evgreen@chromium.org/ Signed-off-by: Marc Gonzalez Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 75f443d598ff..2658100378e0 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1144,6 +1144,7 @@ ufshc: ufshc@1da4000 { phy-names = "ufsphy"; lanes-per-direction = <2>; power-domains = <&gcc UFS_GDSC>; + #reset-cells = <1>; clock-names = "core_clk", @@ -1191,6 +1192,9 @@ ufsphy: phy@1da7000 { <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_AUX_CLK>; + reset-names = "ufsphy"; + resets = <&ufshc 0>; + ufsphy_lanes: lanes@1da7400 { reg = <0x01da7400 0x128>, <0x01da7600 0x1fc>, From 136e9d920dc616f74642efaf1413f82096ddd989 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Tue, 5 Mar 2019 19:53:13 -0500 Subject: [PATCH 29/38] arm64: dts: qcom: pm8005: add gpio-ranges This adds the gpio-ranges property so that the GPIO pins are initialized by the GPIO framework and not pinctrl. This fixes a circular dependency between these two frameworks so GPIO hogging can be used on this board. This was not tested on this particular hardware, however this same change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pm8005.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi index c0ddf128136c..3f97607d8baa 100644 --- a/arch/arm64/boot/dts/qcom/pm8005.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8005.dtsi @@ -15,6 +15,7 @@ pm8005_gpio: gpios@c000 { compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8005_gpio 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; From 99c70e7286237ea0701523555623faf6b49ce0db Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Tue, 5 Mar 2019 19:53:14 -0500 Subject: [PATCH 30/38] arm64: dts: qcom: pm8998: add gpio-ranges This adds the gpio-ranges property so that the GPIO pins are initialized by the GPIO framework and not pinctrl. This fixes a circular dependency between these two frameworks so GPIO hogging can be used on this board. This was not tested on this particular hardware, however this same change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pm8998.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 43cb5ea14089..4872f116758d 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -93,6 +93,7 @@ pm8998_gpio: gpios@c000 { compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8998_gpio 0 0 26>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; From 21750eb93ea9ebe445c922f5319c6b490f45f70d Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Tue, 5 Mar 2019 19:53:15 -0500 Subject: [PATCH 31/38] arm64: dts: qcom: pmi8994: add gpio-ranges This adds the gpio-ranges property so that the GPIO pins are initialized by the GPIO framework and not pinctrl. This fixes a circular dependency between these two frameworks so GPIO hogging can be used on this board. This was not tested on this particular hardware, however this same change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pmi8994.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index 3aee10e3f921..21e05215abe4 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -14,6 +14,7 @@ pmi8994_gpios: gpios@c000 { compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pmi8994_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; From d1fe337337edd37233e2fe65a43e7da6155fbec6 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Tue, 5 Mar 2019 19:53:16 -0500 Subject: [PATCH 32/38] arm64: dts: qcom: pmi8998: add gpio-ranges This adds the gpio-ranges property so that the GPIO pins are initialized by the GPIO framework and not pinctrl. This fixes a circular dependency between these two frameworks so GPIO hogging can be used on this board. This was not tested on this particular hardware, however this same change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 051f57e7d6ac..23f9146a161e 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -13,6 +13,7 @@ pmi8998_gpio: gpios@c000 { compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pmi8998_gpio 0 0 14>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; From 3efd4352ba7c1b8c383321aaf9e27feade0f5e3f Mon Sep 17 00:00:00 2001 From: Khasim Syed Mohammed Date: Mon, 4 Mar 2019 21:14:24 +0100 Subject: [PATCH 33/38] arm64: dts: qcom: qcs404-evb: Change the compatible to distinguish platforms The compatible flag should be different for each board to match with the dtb and to let the bootloader pick the appropriate dtb. Signed-off-by: Khasim Syed Mohammed Signed-off-by: Niklas Cassel Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts | 3 ++- arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts index 2c14903d808e..937eb4555ffe 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts +++ b/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts @@ -7,5 +7,6 @@ / { model = "Qualcomm Technologies, Inc. QCS404 EVB 1000"; - compatible = "qcom,qcs404-evb"; + compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", + "qcom,qcs404"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts index 8234cff414de..479ad3ac6c28 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts +++ b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts @@ -8,7 +8,8 @@ / { model = "Qualcomm Technologies, Inc. QCS404 EVB 4000"; - compatible = "qcom,qcs404-evb"; + compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", + "qcom,qcs404"; }; ðernet { From c8be55410474360e9c791c3cbab42be4e498f363 Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Fri, 5 Apr 2019 12:36:27 +0200 Subject: [PATCH 34/38] arm64: dts: qcom: msm8998: Fix blsp2_i2c5 address blsp1_i2c1 is at 0x0c175000 blsp2_i2c5 is at 0x0c1ba000 (the label is correct) Fixes: 1e71d0c273d0a ("arm64: dts: qcom: msm8998: Enumerate i2c controllers") Signed-off-by: Marc Gonzalez Reviewed-by: Jeffrey Hugo Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 2658100378e0..32ed67cb1f97 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1041,7 +1041,7 @@ blsp2_i2c4: i2c@c1b9000 { blsp2_i2c5: i2c@c1ba000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c175000 0x600>; + reg = <0x0c1ba000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, From 71278b058a9f8752e51030e363b7a7306938f64e Mon Sep 17 00:00:00 2001 From: Evan Green Date: Thu, 21 Mar 2019 10:17:56 -0700 Subject: [PATCH 35/38] arm64: dts: sdm845: Add UFS PHY reset Wire up the reset controller in the Qcom UFS controller for the PHY. This will be used to toggle PHY reset during initialization of the PHY. Reviewed-by: Stephen Boyd Signed-off-by: Evan Green Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d8d381f9ca73..84a57d390b6d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1035,6 +1035,7 @@ ufs_mem_hc: ufshc@1d84000 { phy-names = "ufsphy"; lanes-per-direction = <2>; power-domains = <&gcc UFS_PHY_GDSC>; + #reset-cells = <1>; iommus = <&apps_smmu 0x100 0xf>; @@ -1080,6 +1081,8 @@ ufs_mem_phy: phy@1d87000 { clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; status = "disabled"; ufs_mem_phy_lanes: lanes@1d87400 { From a23b5378b26cbee5dcf3b3df3b0f5f533162ccb6 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 5 Feb 2019 21:13:28 -0800 Subject: [PATCH 36/38] arm64: dts: qcom: sdm845: Update reserved memory map Update existing and add missing regions to the reserved memory map, as described in version 10. Reviewed-by: Sibi Sankar Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 74 +++++++++++++++++++++++++--- 1 file changed, 67 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 84a57d390b6d..d313dfdc561b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -75,29 +75,69 @@ reserved-memory { #size-cells = <2>; ranges; - memory@85fc0000 { + hyp_mem: memory@85700000 { + reg = <0 0x85700000 0 0x600000>; + no-map; + }; + + xbl_mem: memory@85e00000 { + reg = <0 0x85e00000 0 0x100000>; + no-map; + }; + + aop_mem: memory@85fc0000 { reg = <0 0x85fc0000 0 0x20000>; no-map; }; - memory@85fe0000 { + aop_cmd_db_mem: memory@85fe0000 { compatible = "qcom,cmd-db"; - reg = <0x0 0x85fe0000 0x0 0x20000>; + reg = <0x0 0x85fe0000 0 0x20000>; no-map; }; smem_mem: memory@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; + reg = <0x0 0x86000000 0 0x200000>; no-map; }; - memory@86200000 { + tz_mem: memory@86200000 { reg = <0 0x86200000 0 0x2d00000>; no-map; }; - wlan_msa_mem: memory@96700000 { - reg = <0 0x96700000 0 0x100000>; + qseecom_mem: memory@8ab00000 { + reg = <0 0x8ab00000 0 0x1400000>; + no-map; + }; + + camera_mem: memory@8bf00000 { + reg = <0 0x8bf00000 0 0x500000>; + no-map; + }; + + ipa_fw_mem: memory@8c400000 { + reg = <0 0x8c400000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: memory@8c410000 { + reg = <0 0x8c410000 0 0x5000>; + no-map; + }; + + gpu_mem: memory@8c415000 { + reg = <0 0x8c415000 0 0x2000>; + no-map; + }; + + adsp_mem: memory@8c500000 { + reg = <0 0x8c500000 0 0x1a00000>; + no-map; + }; + + wlan_msa_mem: memory@8df00000 { + reg = <0 0x8df00000 0 0x100000>; no-map; }; @@ -106,10 +146,30 @@ mpss_region: memory@8e000000 { no-map; }; + venus_mem: memory@95800000 { + reg = <0 0x95800000 0 0x500000>; + no-map; + }; + + cdsp_mem: memory@95d00000 { + reg = <0 0x95d00000 0 0x800000>; + no-map; + }; + mba_region: memory@96500000 { reg = <0 0x96500000 0 0x200000>; no-map; }; + + slpi_mem: memory@96700000 { + reg = <0 0x96700000 0 0x1400000>; + no-map; + }; + + spss_mem: memory@97b00000 { + reg = <0 0x97b00000 0 0x100000>; + no-map; + }; }; cpus { From bdecbe6b48a5440dde31274ef7ab44420175c19d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 5 Feb 2019 21:13:29 -0800 Subject: [PATCH 37/38] arm64: dts: qcom: sdm845: Define rmtfs memory Define the rmtfs memory node. As the memory region specified in version 10 of the memory map is only 1MB a chunk of unallocated memory is chosen. Tested-by: Sibi Sankar Reviewed-by: Sibi Sankar Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d313dfdc561b..b943dc343279 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -106,6 +106,15 @@ tz_mem: memory@86200000 { no-map; }; + rmtfs_mem: memory@88f00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0x88f00000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + qseecom_mem: memory@8ab00000 { reg = <0 0x8ab00000 0 0x1400000>; no-map; From 6ef7c11b31a57e43062da15a36fac54fcb97b533 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 5 Feb 2019 21:13:30 -0800 Subject: [PATCH 38/38] arm64: dts: sdm845: Introduce ADSP and CDSP PAS nodes Add the Audio DSP (ADSP) and Compute DSP (CDSP) nodes for TrustZone based remoteproc, supporting booting these cores on e.g. the MTP, and enable the same for the MTP. Tested-by: Sibi Sankar Reviewed-by: Sibi Sankar Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 8 ++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 58 +++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index af8c6a2445a2..02b8357c8ce8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -48,6 +48,10 @@ vreg_s4a_1p8: pm8998-smps4 { }; }; +&adsp_pas { + status = "okay"; +}; + &apps_rsc { pm8998-rpmh-regulators { compatible = "qcom,pm8998-rpmh-regulators"; @@ -344,6 +348,10 @@ vreg_s3c_0p6: smps3 { }; }; +&cdsp_pas { + status = "okay"; +}; + &gcc { protected-clocks = , , diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b943dc343279..dd67f9c5cb43 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -335,6 +335,64 @@ scm { }; }; + adsp_pas: remoteproc-adsp { + compatible = "qcom,sdm845-adsp-pas"; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + memory-region = <&adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apss_shared 8>; + }; + }; + + cdsp_pas: remoteproc-cdsp { + compatible = "qcom,sdm845-cdsp-pas"; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + memory-region = <&cdsp_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "turing"; + qcom,remote-pid = <5>; + mboxes = <&apss_shared 4>; + }; + }; + tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_regs 0 0x1000>;