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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 01:26:43 +07:00
net/mlx5: DR, Remove unneeded check from source port builder
Mask validity for ste builders is checked by mlx5dr_ste_build_pre_check during matcher creation. It already checks the mask value of source_vport, so removing this duplicated check. Also, moving there the check of source_eswitch_owner_vhca_id mask. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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97ffd895fe
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@ -252,10 +252,8 @@ static int dr_matcher_set_ste_builders(struct mlx5dr_matcher *matcher,
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if (dr_mask_is_gvmi_or_qpn_set(&mask.misc) &&
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(dmn->type == MLX5DR_DOMAIN_TYPE_FDB ||
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dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX)) {
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ret = mlx5dr_ste_build_src_gvmi_qpn(&sb[idx++], &mask,
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dmn, inner, rx);
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if (ret)
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return ret;
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mlx5dr_ste_build_src_gvmi_qpn(&sb[idx++], &mask,
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dmn, inner, rx);
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}
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if (dr_mask_is_smac_set(&mask.outer) &&
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@ -709,7 +709,14 @@ int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn,
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{
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if (!value && (match_criteria & DR_MATCHER_CRITERIA_MISC)) {
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if (mask->misc.source_port && mask->misc.source_port != 0xffff) {
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mlx5dr_err(dmn, "Partial mask source_port is not supported\n");
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mlx5dr_err(dmn,
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"Partial mask source_port is not supported\n");
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return -EINVAL;
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}
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if (mask->misc.source_eswitch_owner_vhca_id &&
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mask->misc.source_eswitch_owner_vhca_id != 0xffff) {
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mlx5dr_err(dmn,
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"Partial mask source_eswitch_owner_vhca_id is not supported\n");
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return -EINVAL;
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}
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}
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@ -2257,25 +2264,14 @@ void mlx5dr_ste_build_register_1(struct mlx5dr_ste_build *sb,
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sb->ste_build_tag_func = &dr_ste_build_register_1_tag;
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}
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static int dr_ste_build_src_gvmi_qpn_bit_mask(struct mlx5dr_match_param *value,
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u8 *bit_mask)
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static void dr_ste_build_src_gvmi_qpn_bit_mask(struct mlx5dr_match_param *value,
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u8 *bit_mask)
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{
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struct mlx5dr_match_misc *misc_mask = &value->misc;
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/* Partial misc source_port is not supported */
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if (misc_mask->source_port && misc_mask->source_port != 0xffff)
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return -EINVAL;
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/* Partial misc source_eswitch_owner_vhca_id is not supported */
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if (misc_mask->source_eswitch_owner_vhca_id &&
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misc_mask->source_eswitch_owner_vhca_id != 0xffff)
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return -EINVAL;
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DR_STE_SET_MASK(src_gvmi_qp, bit_mask, source_gvmi, misc_mask, source_port);
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DR_STE_SET_MASK(src_gvmi_qp, bit_mask, source_qp, misc_mask, source_sqn);
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misc_mask->source_eswitch_owner_vhca_id = 0;
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return 0;
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}
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static int dr_ste_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value,
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@ -2320,19 +2316,15 @@ static int dr_ste_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value,
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return 0;
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}
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int mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_build *sb,
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struct mlx5dr_match_param *mask,
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struct mlx5dr_domain *dmn,
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bool inner, bool rx)
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void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_build *sb,
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struct mlx5dr_match_param *mask,
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struct mlx5dr_domain *dmn,
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bool inner, bool rx)
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{
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int ret;
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/* Set vhca_id_valid before we reset source_eswitch_owner_vhca_id */
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sb->vhca_id_valid = mask->misc.source_eswitch_owner_vhca_id;
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ret = dr_ste_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask);
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if (ret)
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return ret;
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dr_ste_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask);
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sb->rx = rx;
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sb->dmn = dmn;
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@ -2340,6 +2332,4 @@ int mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_build *sb,
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sb->lu_type = MLX5DR_STE_LU_TYPE_SRC_GVMI_AND_QP;
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sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
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sb->ste_build_tag_func = &dr_ste_build_src_gvmi_qpn_tag;
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return 0;
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}
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@ -346,10 +346,10 @@ void mlx5dr_ste_build_register_0(struct mlx5dr_ste_build *sb,
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void mlx5dr_ste_build_register_1(struct mlx5dr_ste_build *sb,
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struct mlx5dr_match_param *mask,
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bool inner, bool rx);
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int mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_build *sb,
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struct mlx5dr_match_param *mask,
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struct mlx5dr_domain *dmn,
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bool inner, bool rx);
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void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_build *sb,
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struct mlx5dr_match_param *mask,
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struct mlx5dr_domain *dmn,
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bool inner, bool rx);
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void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx);
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/* Actions utils */
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