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ARM: dts: Add the Gemini reset controller

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This adds the Gemini reset controller to the Gemini SoC
DTSI file and also adds the reset references to all existing
blocks already in the device tree.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij 2017-04-13 16:09:53 +02:00
parent a87af2db72
commit 3863c52899
1 changed files with 12 additions and 1 deletions
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13
arch/arm/boot/dts/gemini.dtsi
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@ -25,8 +25,10 @@ flash@30000000 {
};
syscon: syscon@40000000 {
compatible = "cortina,gemini-syscon", "syscon", "simple-mfd";
compatible = "cortina,gemini-syscon",
"syscon", "simple-mfd";
reg = <0x40000000 0x1000>;
#reset-cells = <1>;
syscon-reboot {
compatible = "syscon-reboot";
@ -42,11 +44,13 @@ watchdog@41000000 {
compatible = "cortina,gemini-watchdog";
reg = <0x41000000 0x1000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon 23>;
};
uart0: serial@42000000 {
compatible = "ns16550a";
reg = <0x42000000 0x100>;
resets = <&syscon 18>;
clock-frequency = <48000000>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@ -59,6 +63,7 @@ timer@43000000 {
interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
resets = <&syscon 17>;
syscon = <&syscon>;
};
@ -66,11 +71,13 @@ rtc@45000000 {
compatible = "cortina,gemini-rtc";
reg = <0x45000000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon 16>;
};
intcon: interrupt-controller@48000000 {
compatible = "faraday,ftintc010";
reg = <0x48000000 0x1000>;
resets = <&syscon 14>;
interrupt-controller;
#interrupt-cells = <2>;
};
@ -85,6 +92,7 @@ gpio0: gpio@4d000000 {
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4d000000 0x100>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon 20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -95,6 +103,7 @@ gpio1: gpio@4e000000 {
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4e000000 0x100>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon 21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -105,6 +114,7 @@ gpio2: gpio@4f000000 {
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4f000000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon 22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -118,6 +128,7 @@ pci@50000000 {
* to configure the host bridge.
*/
reg = <0x50000000 0x100>;
resets = <&syscon 7>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;