AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-26 18:10:51 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

clk: tegra: Constify pdiv-to-hw mappings

Browse Source 
This is static data that is never modified, so make it const.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2015-11-19 16:34:06 +01:00
parent 8d99704fde
commit 385f9adf62
6 changed files with 15 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/clk/tegra/clk-pll.c
View File

@ -359,7 +359,7 @@ static void clk_pll_disable(struct clk_hw *hw)
static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
if (p_tohw) {
while (p_tohw->pdiv) {
@ -375,7 +375,7 @@ static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
if (p_tohw) {
while (p_tohw->pdiv) {
@ -1700,7 +1700,7 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
spinlock_t *lock)
{
struct clk *parent, *clk;
struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
struct tegra_clk_pll *pll;
struct tegra_clk_pll_freq_table cfg;
unsigned long parent_rate;

8
drivers/clk/tegra/clk-tegra114.c
View File

@ -182,7 +182,7 @@ static struct div_nmp pllxc_nmp = {
.divp_width = 4,
};
static struct pdiv_map pllxc_p[] = {
static const struct pdiv_map pllxc_p[] = {
{ .pdiv = 1, .hw_val = 0 },
{ .pdiv = 2, .hw_val = 1 },
{ .pdiv = 3, .hw_val = 2 },
@ -244,7 +244,7 @@ static struct div_nmp pllcx_nmp = {
.divp_width = 3,
};
static struct pdiv_map pllc_p[] = {
static const struct pdiv_map pllc_p[] = {
{ .pdiv = 1, .hw_val = 0 },
{ .pdiv = 2, .hw_val = 1 },
{ .pdiv = 4, .hw_val = 3 },
@ -318,7 +318,7 @@ static struct div_nmp pllm_nmp = {
.override_divp_shift = 27,
};
static struct pdiv_map pllm_p[] = {
static const struct pdiv_map pllm_p[] = {
{ .pdiv = 1, .hw_val = 0 },
{ .pdiv = 2, .hw_val = 1 },
{ .pdiv = 0, .hw_val = 0 },
@ -472,7 +472,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
TEGRA_PLL_USE_LOCK,
};
static struct pdiv_map pllu_p[] = {
static const struct pdiv_map pllu_p[] = {
{ .pdiv = 1, .hw_val = 1 },
{ .pdiv = 2, .hw_val = 0 },
{ .pdiv = 0, .hw_val = 0 },

10
drivers/clk/tegra/clk-tegra124.c
View File

@ -168,7 +168,7 @@ static struct div_nmp pllxc_nmp = {
.divp_width = 4,
};
static struct pdiv_map pllxc_p[] = {
static const struct pdiv_map pllxc_p[] = {
{ .pdiv = 1, .hw_val = 0 },
{ .pdiv = 2, .hw_val = 1 },
{ .pdiv = 3, .hw_val = 2 },
@ -264,7 +264,7 @@ static struct div_nmp pllcx_nmp = {
.divp_width = 3,
};
static struct pdiv_map pllc_p[] = {
static const struct pdiv_map pllc_p[] = {
{ .pdiv = 1, .hw_val = 0 },
{ .pdiv = 2, .hw_val = 1 },
{ .pdiv = 3, .hw_val = 2 },
@ -338,7 +338,7 @@ static struct div_nmp pllss_nmp = {
.divp_width = 4,
};
static struct pdiv_map pll12g_ssd_esd_p[] = {
static const struct pdiv_map pll12g_ssd_esd_p[] = {
{ .pdiv = 1, .hw_val = 0 },
{ .pdiv = 2, .hw_val = 1 },
{ .pdiv = 3, .hw_val = 2 },
@ -388,7 +388,7 @@ static struct tegra_clk_pll_params pll_c4_params = {
.freq_table = pll_c4_freq_table,
};
static struct pdiv_map pllm_p[] = {
static const struct pdiv_map pllm_p[] = {
{ .pdiv = 1, .hw_val = 0 },
{ .pdiv = 2, .hw_val = 1 },
{ .pdiv = 0, .hw_val = 0 },
@ -682,7 +682,7 @@ static struct tegra_clk_pll_params pll_dp_params = {
.freq_table = pll_dp_freq_table,
};
static struct pdiv_map pllu_p[] = {
static const struct pdiv_map pllu_p[] = {
{ .pdiv = 1, .hw_val = 1 },
{ .pdiv = 2, .hw_val = 0 },
{ .pdiv = 0, .hw_val = 0 },

2
drivers/clk/tegra/clk-tegra20.c
View File

@ -359,7 +359,7 @@ static struct tegra_clk_pll_params pll_d_params = {
.flags = TEGRA_PLL_HAS_CPCON,
};
static struct pdiv_map pllu_p[] = {
static const struct pdiv_map pllu_p[] = {
{ .pdiv = 1, .hw_val = 1 },
{ .pdiv = 2, .hw_val = 0 },
{ .pdiv = 0, .hw_val = 0 },

2
drivers/clk/tegra/clk-tegra30.c
View File

@ -332,7 +332,7 @@ static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
{ 0, 0, 0, 0, 0, 0 },
};
static struct pdiv_map pllu_p[] = {
static const struct pdiv_map pllu_p[] = {
{ .pdiv = 1, .hw_val = 1 },
{ .pdiv = 2, .hw_val = 0 },
{ .pdiv = 0, .hw_val = 0 },

2
drivers/clk/tegra/clk.h
View File

@ -233,7 +233,7 @@ struct tegra_clk_pll_params {
int stepb_shift;
int lock_delay;
int max_p;
struct pdiv_map *pdiv_tohw;
const struct pdiv_map *pdiv_tohw;
struct div_nmp *div_nmp;
struct tegra_clk_pll_freq_table *freq_table;
unsigned long fixed_rate;