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powerpc/64s: Fix data interrupts vs d-side MCE reentrancy
Handlers for interrupts that set DAR / DSISR, set MSR[RI] before those SPRs are read. If a d-side machine check hits in this window, DAR / DSISR will be clobbered silently, leading to random corruption. Fix this by having handlers save those registers before setting MSR[RI]. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -582,12 +582,25 @@ EXC_REAL_END(data_access, 0x300, 0x80)
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TRAMP_REAL_BEGIN(tramp_real_data_access)
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EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, 0x300)
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/*
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* DAR/DSISR must be read before setting MSR[RI], because
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* a d-side MCE will clobber those registers so is not
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* recoverable if they are live.
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*/
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mfspr r10,SPRN_DAR
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mfspr r11,SPRN_DSISR
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std r10,PACA_EXGEN+EX_DAR(r13)
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stw r11,PACA_EXGEN+EX_DSISR(r13)
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EXCEPTION_PROLOG_2(data_access_common, EXC_STD)
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EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
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SET_SCRATCH0(r13) /* save r13 */
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EXCEPTION_PROLOG_0(PACA_EXGEN)
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EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x300)
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mfspr r10,SPRN_DAR
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mfspr r11,SPRN_DSISR
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std r10,PACA_EXGEN+EX_DAR(r13)
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stw r11,PACA_EXGEN+EX_DSISR(r13)
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EXCEPTION_PROLOG_2_RELON(data_access_common, EXC_STD)
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EXC_VIRT_END(data_access, 0x4300, 0x80)
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@ -598,11 +611,8 @@ EXC_COMMON_BEGIN(data_access_common)
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* Here r13 points to the paca, r9 contains the saved CR,
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* SRR0 and SRR1 are saved in r11 and r12,
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* r9 - r13 are saved in paca->exgen.
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* EX_DAR and EX_DSISR have saved DAR/DSISR
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*/
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mfspr r10,SPRN_DAR
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std r10,PACA_EXGEN+EX_DAR(r13)
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mfspr r10,SPRN_DSISR
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stw r10,PACA_EXGEN+EX_DSISR(r13)
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EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
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RECONCILE_IRQ_STATE(r10, r11)
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ld r12,_MSR(r1)
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@ -626,20 +636,22 @@ EXC_REAL_END(data_access_slb, 0x380, 0x80)
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TRAMP_REAL_BEGIN(tramp_real_data_access_slb)
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EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
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mfspr r10,SPRN_DAR
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std r10,PACA_EXSLB+EX_DAR(r13)
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EXCEPTION_PROLOG_2(data_access_slb_common, EXC_STD)
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EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
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SET_SCRATCH0(r13) /* save r13 */
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EXCEPTION_PROLOG_0(PACA_EXSLB)
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EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
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mfspr r10,SPRN_DAR
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std r10,PACA_EXSLB+EX_DAR(r13)
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EXCEPTION_PROLOG_2_RELON(data_access_slb_common, EXC_STD)
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EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
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TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
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EXC_COMMON_BEGIN(data_access_slb_common)
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mfspr r10,SPRN_DAR
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std r10,PACA_EXSLB+EX_DAR(r13)
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EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
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ld r4,PACA_EXSLB+EX_DAR(r13)
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std r4,_DAR(r1)
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@ -739,6 +751,10 @@ EXC_REAL_BEGIN(alignment, 0x600, 0x100)
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SET_SCRATCH0(r13) /* save r13 */
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EXCEPTION_PROLOG_0(PACA_EXGEN)
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EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, 0x600)
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mfspr r10,SPRN_DAR
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mfspr r11,SPRN_DSISR
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std r10,PACA_EXGEN+EX_DAR(r13)
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stw r11,PACA_EXGEN+EX_DSISR(r13)
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EXCEPTION_PROLOG_2(alignment_common, EXC_STD)
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EXC_REAL_END(alignment, 0x600, 0x100)
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@ -746,15 +762,15 @@ EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
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SET_SCRATCH0(r13) /* save r13 */
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EXCEPTION_PROLOG_0(PACA_EXGEN)
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EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x600)
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mfspr r10,SPRN_DAR
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mfspr r11,SPRN_DSISR
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std r10,PACA_EXGEN+EX_DAR(r13)
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stw r11,PACA_EXGEN+EX_DSISR(r13)
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EXCEPTION_PROLOG_2_RELON(alignment_common, EXC_STD)
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EXC_VIRT_END(alignment, 0x4600, 0x100)
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TRAMP_KVM(PACA_EXGEN, 0x600)
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EXC_COMMON_BEGIN(alignment_common)
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mfspr r10,SPRN_DAR
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std r10,PACA_EXGEN+EX_DAR(r13)
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mfspr r10,SPRN_DSISR
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stw r10,PACA_EXGEN+EX_DSISR(r13)
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EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
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ld r3,PACA_EXGEN+EX_DAR(r13)
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lwz r4,PACA_EXGEN+EX_DSISR(r13)
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