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drm/i915: Don't fiddle with rps/rc6 across GPU reset

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Resetting the GPU doesn't affect the RPS/RC6 state, so we can stop
forcibly reloading the registers.

Ville suggested this many moons ago, I said at that time that sanitizing
was no harm and meant that our bookkeeping was kept consistent with the
HW. However, in a forthcoming series, we want to split rps/rc6 GT
powermanagement and one of the key simplifications is the control of
when we enable it. Performing a crude sanitize in the middle of
i915_gem_reset() is then a huge wart.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180410133354.13425-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson 2018-04-10 14:33:54 +01:00
parent d52ad9cb9d
commit 3834dc1f0e
1 changed files with 0 additions and 7 deletions
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7
drivers/gpu/drm/i915/i915_gem.c
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@ -3254,13 +3254,6 @@ void i915_gem_reset(struct drm_i915_private *dev_priv,
}
i915_gem_restore_fences(dev_priv);
if (dev_priv->gt.awake) {
intel_sanitize_gt_powersave(dev_priv);
intel_enable_gt_powersave(dev_priv);
if (INTEL_GEN(dev_priv) >= 6)
gen6_rps_busy(dev_priv);
}
}
void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)