mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 09:40:58 +07:00
ARM: mmp: Remove legacy clk code
Remove all the legacy clk code that supports a non-common clk framework
implementation of 'struct clk' in mach-mmp. This code doesn't look to be
compiled anymore given that the MMP is fully supported in the
multi-platform config via ARCH_MULTIPLATFORM as of commit 377524dc4d
("ARM: mmp: move into ARCH_MULTIPLATFORM"). The ARCH_MULTIPLATFORM
config selects COMMON_CLK and therefore the Makefile rule can never
actually compile the code in these files.
Cc: Lubomir Rintel <lkundrak@v3.sk>
Cc: Russell King <linux@armlinux.org.uk>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200409064416.83340-9-sboyd@kernel.org
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
[sboyd@kernel.org: Squash in a clock.h include removal found by Stephen
Rothwell <sfr@canb.auug.org.au>]
This commit is contained in:
Stephen Boyd
parent
bbd7ffdbef
commit
3819ad4402
@ -12,12 +12,6 @@ obj-$(CONFIG_CPU_PXA910) += pxa910.o
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obj-$(CONFIG_CPU_MMP2) += mmp2.o
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obj-$(CONFIG_MMP_SRAM) += sram.o
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ifeq ($(CONFIG_COMMON_CLK), )
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obj-y += clock.o
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obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o
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obj-$(CONFIG_CPU_PXA910) += clock-pxa910.o
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obj-$(CONFIG_CPU_MMP2) += clock-mmp2.o
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endif
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ifeq ($(CONFIG_PM),y)
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obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
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obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o
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@ -1,114 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clk/mmp.h>
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#include "addr-map.h"
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#include "common.h"
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#include "clock.h"
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/*
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* APB Clock register offsets for MMP2
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*/
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#define APBC_RTC APBC_REG(0x000)
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#define APBC_TWSI1 APBC_REG(0x004)
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#define APBC_TWSI2 APBC_REG(0x008)
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#define APBC_TWSI3 APBC_REG(0x00c)
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#define APBC_TWSI4 APBC_REG(0x010)
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#define APBC_KPC APBC_REG(0x018)
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#define APBC_UART1 APBC_REG(0x02c)
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#define APBC_UART2 APBC_REG(0x030)
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#define APBC_UART3 APBC_REG(0x034)
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#define APBC_GPIO APBC_REG(0x038)
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#define APBC_PWM0 APBC_REG(0x03c)
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#define APBC_PWM1 APBC_REG(0x040)
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#define APBC_PWM2 APBC_REG(0x044)
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#define APBC_PWM3 APBC_REG(0x048)
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#define APBC_SSP0 APBC_REG(0x04c)
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#define APBC_SSP1 APBC_REG(0x050)
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#define APBC_SSP2 APBC_REG(0x054)
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#define APBC_SSP3 APBC_REG(0x058)
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#define APBC_SSP4 APBC_REG(0x05c)
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#define APBC_SSP5 APBC_REG(0x060)
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#define APBC_TWSI5 APBC_REG(0x07c)
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#define APBC_TWSI6 APBC_REG(0x080)
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#define APBC_UART4 APBC_REG(0x088)
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#define APMU_USB APMU_REG(0x05c)
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#define APMU_NAND APMU_REG(0x060)
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#define APMU_SDH0 APMU_REG(0x054)
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#define APMU_SDH1 APMU_REG(0x058)
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#define APMU_SDH2 APMU_REG(0x0e8)
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#define APMU_SDH3 APMU_REG(0x0ec)
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static void sdhc_clk_enable(struct clk *clk)
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{
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uint32_t clk_rst;
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clk_rst = __raw_readl(clk->clk_rst);
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clk_rst |= clk->enable_val;
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__raw_writel(clk_rst, clk->clk_rst);
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}
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static void sdhc_clk_disable(struct clk *clk)
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{
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uint32_t clk_rst;
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clk_rst = __raw_readl(clk->clk_rst);
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clk_rst &= ~clk->enable_val;
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__raw_writel(clk_rst, clk->clk_rst);
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}
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struct clkops sdhc_clk_ops = {
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.enable = sdhc_clk_enable,
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.disable = sdhc_clk_disable,
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};
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/* APB peripheral clocks */
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static APBC_CLK(uart1, UART1, 1, 26000000);
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static APBC_CLK(uart2, UART2, 1, 26000000);
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static APBC_CLK(uart3, UART3, 1, 26000000);
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static APBC_CLK(uart4, UART4, 1, 26000000);
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static APBC_CLK(twsi1, TWSI1, 0, 26000000);
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static APBC_CLK(twsi2, TWSI2, 0, 26000000);
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static APBC_CLK(twsi3, TWSI3, 0, 26000000);
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static APBC_CLK(twsi4, TWSI4, 0, 26000000);
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static APBC_CLK(twsi5, TWSI5, 0, 26000000);
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static APBC_CLK(twsi6, TWSI6, 0, 26000000);
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static APBC_CLK(gpio, GPIO, 0, 26000000);
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static APMU_CLK(nand, NAND, 0xbf, 100000000);
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static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
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static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
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static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
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static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
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static struct clk_lookup mmp2_clkregs[] = {
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INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
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INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
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INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
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INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
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INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
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INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
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INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
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INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
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INIT_CLKREG(&clk_gpio, "mmp2-gpio", NULL),
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INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
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INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
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INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
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INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
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};
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void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
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phys_addr_t apbc_phys)
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{
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clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
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}
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@ -1,94 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clk/mmp.h>
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#include "addr-map.h"
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#include "common.h"
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#include "clock.h"
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/*
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* APB clock register offsets for PXA168
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*/
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#define APBC_UART1 APBC_REG(0x000)
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#define APBC_UART2 APBC_REG(0x004)
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#define APBC_GPIO APBC_REG(0x008)
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#define APBC_PWM1 APBC_REG(0x00c)
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#define APBC_PWM2 APBC_REG(0x010)
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#define APBC_PWM3 APBC_REG(0x014)
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#define APBC_PWM4 APBC_REG(0x018)
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#define APBC_RTC APBC_REG(0x028)
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#define APBC_TWSI0 APBC_REG(0x02c)
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#define APBC_KPC APBC_REG(0x030)
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#define APBC_TWSI1 APBC_REG(0x06c)
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#define APBC_UART3 APBC_REG(0x070)
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#define APBC_SSP1 APBC_REG(0x81c)
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#define APBC_SSP2 APBC_REG(0x820)
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#define APBC_SSP3 APBC_REG(0x84c)
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#define APBC_SSP4 APBC_REG(0x858)
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#define APBC_SSP5 APBC_REG(0x85c)
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#define APMU_NAND APMU_REG(0x060)
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#define APMU_LCD APMU_REG(0x04c)
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#define APMU_ETH APMU_REG(0x0fc)
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#define APMU_USB APMU_REG(0x05c)
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/* APB peripheral clocks */
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static APBC_CLK(uart1, UART1, 1, 14745600);
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static APBC_CLK(uart2, UART2, 1, 14745600);
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static APBC_CLK(uart3, UART3, 1, 14745600);
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static APBC_CLK(twsi0, TWSI0, 1, 33000000);
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static APBC_CLK(twsi1, TWSI1, 1, 33000000);
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static APBC_CLK(pwm1, PWM1, 1, 13000000);
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static APBC_CLK(pwm2, PWM2, 1, 13000000);
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static APBC_CLK(pwm3, PWM3, 1, 13000000);
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static APBC_CLK(pwm4, PWM4, 1, 13000000);
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static APBC_CLK(ssp1, SSP1, 4, 0);
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static APBC_CLK(ssp2, SSP2, 4, 0);
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static APBC_CLK(ssp3, SSP3, 4, 0);
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static APBC_CLK(ssp4, SSP4, 4, 0);
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static APBC_CLK(ssp5, SSP5, 4, 0);
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static APBC_CLK(gpio, GPIO, 0, 13000000);
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static APBC_CLK(keypad, KPC, 0, 32000);
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static APBC_CLK(rtc, RTC, 8, 32768);
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static APMU_CLK(nand, NAND, 0x19b, 156000000);
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static APMU_CLK(lcd, LCD, 0x7f, 312000000);
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static APMU_CLK(eth, ETH, 0x09, 0);
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static APMU_CLK(usb, USB, 0x12, 0);
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/* device and clock bindings */
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static struct clk_lookup pxa168_clkregs[] = {
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INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
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INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
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INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
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INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
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INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
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INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
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INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
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INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
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INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
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INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
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INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
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INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
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INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
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INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL),
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INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
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INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
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INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
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INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
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};
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void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
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phys_addr_t apbc_phys)
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{
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clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
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}
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@ -1,70 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clk/mmp.h>
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#include "addr-map.h"
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#include "common.h"
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#include "clock.h"
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/*
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* APB Clock register offsets for PXA910
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*/
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#define APBC_UART0 APBC_REG(0x000)
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#define APBC_UART1 APBC_REG(0x004)
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#define APBC_GPIO APBC_REG(0x008)
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#define APBC_PWM1 APBC_REG(0x00c)
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#define APBC_PWM2 APBC_REG(0x010)
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#define APBC_PWM3 APBC_REG(0x014)
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#define APBC_PWM4 APBC_REG(0x018)
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#define APBC_SSP1 APBC_REG(0x01c)
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#define APBC_SSP2 APBC_REG(0x020)
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#define APBC_RTC APBC_REG(0x028)
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#define APBC_TWSI0 APBC_REG(0x02c)
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#define APBC_KPC APBC_REG(0x030)
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#define APBC_SSP3 APBC_REG(0x04c)
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#define APBC_TWSI1 APBC_REG(0x06c)
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#define APMU_NAND APMU_REG(0x060)
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#define APMU_USB APMU_REG(0x05c)
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static APBC_CLK(uart1, UART0, 1, 14745600);
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static APBC_CLK(uart2, UART1, 1, 14745600);
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static APBC_CLK(twsi0, TWSI0, 1, 33000000);
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static APBC_CLK(twsi1, TWSI1, 1, 33000000);
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static APBC_CLK(pwm1, PWM1, 1, 13000000);
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static APBC_CLK(pwm2, PWM2, 1, 13000000);
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static APBC_CLK(pwm3, PWM3, 1, 13000000);
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static APBC_CLK(pwm4, PWM4, 1, 13000000);
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static APBC_CLK(gpio, GPIO, 0, 13000000);
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static APBC_CLK(rtc, RTC, 8, 32768);
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static APMU_CLK(nand, NAND, 0x19b, 156000000);
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static APMU_CLK(u2o, USB, 0x1b, 480000000);
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/* device and clock bindings */
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static struct clk_lookup pxa910_clkregs[] = {
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INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
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INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
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INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
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INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
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INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
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INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
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INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL),
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INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
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INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
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};
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void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
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phys_addr_t apbc_phys, phys_addr_t apbcp_phys)
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{
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clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
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}
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@ -1,105 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* linux/arch/arm/mach-mmp/clock.c
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "regs-apbc.h"
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#include "clock.h"
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static void apbc_clk_enable(struct clk *clk)
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{
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uint32_t clk_rst;
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clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel);
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__raw_writel(clk_rst, clk->clk_rst);
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}
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static void apbc_clk_disable(struct clk *clk)
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{
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__raw_writel(0, clk->clk_rst);
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}
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struct clkops apbc_clk_ops = {
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.enable = apbc_clk_enable,
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.disable = apbc_clk_disable,
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};
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static void apmu_clk_enable(struct clk *clk)
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{
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__raw_writel(clk->enable_val, clk->clk_rst);
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}
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static void apmu_clk_disable(struct clk *clk)
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{
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__raw_writel(0, clk->clk_rst);
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}
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struct clkops apmu_clk_ops = {
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.enable = apmu_clk_enable,
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.disable = apmu_clk_disable,
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};
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static DEFINE_SPINLOCK(clocks_lock);
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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spin_lock_irqsave(&clocks_lock, flags);
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if (clk->enabled++ == 0)
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clk->ops->enable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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||||
|
||||
if (!clk)
|
||||
return;
|
||||
|
||||
WARN_ON(clk->enabled == 0);
|
||||
|
||||
spin_lock_irqsave(&clocks_lock, flags);
|
||||
if (--clk->enabled == 0)
|
||||
clk->ops->disable(clk);
|
||||
spin_unlock_irqrestore(&clocks_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_disable);
|
||||
|
||||
unsigned long clk_get_rate(struct clk *clk)
|
||||
{
|
||||
unsigned long rate;
|
||||
|
||||
if (clk->ops->getrate)
|
||||
rate = clk->ops->getrate(clk);
|
||||
else
|
||||
rate = clk->rate;
|
||||
|
||||
return rate;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_rate);
|
||||
|
||||
int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (clk->ops->setrate) {
|
||||
spin_lock_irqsave(&clocks_lock, flags);
|
||||
ret = clk->ops->setrate(clk, rate);
|
||||
spin_unlock_irqrestore(&clocks_lock, flags);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_rate);
|
||||
@ -1,65 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <linux/clkdev.h>
|
||||
|
||||
struct clkops {
|
||||
void (*enable)(struct clk *);
|
||||
void (*disable)(struct clk *);
|
||||
unsigned long (*getrate)(struct clk *);
|
||||
int (*setrate)(struct clk *, unsigned long);
|
||||
};
|
||||
|
||||
struct clk {
|
||||
const struct clkops *ops;
|
||||
|
||||
void __iomem *clk_rst; /* clock reset control register */
|
||||
int fnclksel; /* functional clock select (APBC) */
|
||||
uint32_t enable_val; /* value for clock enable (APMU) */
|
||||
unsigned long rate;
|
||||
int enabled;
|
||||
};
|
||||
|
||||
extern struct clkops apbc_clk_ops;
|
||||
extern struct clkops apmu_clk_ops;
|
||||
|
||||
#define APBC_CLK(_name, _reg, _fnclksel, _rate) \
|
||||
struct clk clk_##_name = { \
|
||||
.clk_rst = APBC_##_reg, \
|
||||
.fnclksel = _fnclksel, \
|
||||
.rate = _rate, \
|
||||
.ops = &apbc_clk_ops, \
|
||||
}
|
||||
|
||||
#define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \
|
||||
struct clk clk_##_name = { \
|
||||
.clk_rst = APBC_##_reg, \
|
||||
.fnclksel = _fnclksel, \
|
||||
.rate = _rate, \
|
||||
.ops = _ops, \
|
||||
}
|
||||
|
||||
#define APMU_CLK(_name, _reg, _eval, _rate) \
|
||||
struct clk clk_##_name = { \
|
||||
.clk_rst = APMU_##_reg, \
|
||||
.enable_val = _eval, \
|
||||
.rate = _rate, \
|
||||
.ops = &apmu_clk_ops, \
|
||||
}
|
||||
|
||||
#define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \
|
||||
struct clk clk_##_name = { \
|
||||
.clk_rst = APMU_##_reg, \
|
||||
.enable_val = _eval, \
|
||||
.rate = _rate, \
|
||||
.ops = _ops, \
|
||||
}
|
||||
|
||||
#define INIT_CLKREG(_clk, _devname, _conname) \
|
||||
{ \
|
||||
.clk = _clk, \
|
||||
.dev_id = _devname, \
|
||||
.con_id = _conname, \
|
||||
}
|
||||
|
||||
extern struct clk clk_pxa168_gpio;
|
||||
extern struct clk clk_pxa168_timers;
|
||||
@ -19,7 +19,6 @@
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
#include "addr-map.h"
|
||||
#include "clock.h"
|
||||
#include "common.h"
|
||||
#include <linux/soc/mmp/cputype.h>
|
||||
#include "devices.h"
|
||||
|
||||
@ -34,7 +34,6 @@
|
||||
#include "regs-apbc.h"
|
||||
#include "irqs.h"
|
||||
#include <linux/soc/mmp/cputype.h>
|
||||
#include "clock.h"
|
||||
|
||||
#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user