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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 14:06:51 +07:00
drm/radeon/kms/atom: add crtc disable function
Disables the crts as per dpms and also disables the ppll associated with the crtc. This should save additional power. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
90c1efdd12
commit
37f9003bd3
@ -669,6 +669,90 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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static void atombios_crtc_program_pll(struct drm_crtc *crtc,
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int crtc_id,
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int pll_id,
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u32 encoder_mode,
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u32 encoder_id,
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u32 clock,
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u32 ref_div,
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u32 fb_div,
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u32 frac_fb_div,
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u32 post_div)
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{
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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u8 frev, crev;
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int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
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union set_pixel_clock args;
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memset(&args, 0, sizeof(args));
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if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
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&crev))
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return;
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switch (frev) {
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case 1:
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switch (crev) {
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case 1:
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if (clock == ATOM_DISABLE)
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return;
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args.v1.usPixelClock = cpu_to_le16(clock / 10);
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args.v1.usRefDiv = cpu_to_le16(ref_div);
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args.v1.usFbDiv = cpu_to_le16(fb_div);
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args.v1.ucFracFbDiv = frac_fb_div;
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args.v1.ucPostDiv = post_div;
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args.v1.ucPpll = pll_id;
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args.v1.ucCRTC = crtc_id;
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args.v1.ucRefDivSrc = 1;
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break;
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case 2:
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args.v2.usPixelClock = cpu_to_le16(clock / 10);
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args.v2.usRefDiv = cpu_to_le16(ref_div);
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args.v2.usFbDiv = cpu_to_le16(fb_div);
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args.v2.ucFracFbDiv = frac_fb_div;
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args.v2.ucPostDiv = post_div;
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args.v2.ucPpll = pll_id;
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args.v2.ucCRTC = crtc_id;
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args.v2.ucRefDivSrc = 1;
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break;
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case 3:
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args.v3.usPixelClock = cpu_to_le16(clock / 10);
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args.v3.usRefDiv = cpu_to_le16(ref_div);
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args.v3.usFbDiv = cpu_to_le16(fb_div);
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args.v3.ucFracFbDiv = frac_fb_div;
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args.v3.ucPostDiv = post_div;
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args.v3.ucPpll = pll_id;
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args.v3.ucMiscInfo = (pll_id << 2);
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args.v3.ucTransmitterId = encoder_id;
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args.v3.ucEncoderMode = encoder_mode;
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break;
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case 5:
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args.v5.ucCRTC = crtc_id;
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args.v5.usPixelClock = cpu_to_le16(clock / 10);
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args.v5.ucRefDiv = ref_div;
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args.v5.usFbDiv = cpu_to_le16(fb_div);
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args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
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args.v5.ucPostDiv = post_div;
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args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
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args.v5.ucTransmitterID = encoder_id;
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args.v5.ucEncoderMode = encoder_mode;
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args.v5.ucPpll = pll_id;
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break;
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default:
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DRM_ERROR("Unknown table version %d %d\n", frev, crev);
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return;
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}
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break;
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default:
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DRM_ERROR("Unknown table version %d %d\n", frev, crev);
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return;
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}
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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@ -676,17 +760,12 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
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struct radeon_device *rdev = dev->dev_private;
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struct drm_encoder *encoder = NULL;
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struct radeon_encoder *radeon_encoder = NULL;
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u8 frev, crev;
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int index;
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union set_pixel_clock args;
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u32 pll_clock = mode->clock;
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u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
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struct radeon_pll *pll;
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u32 adjusted_clock;
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int encoder_mode = 0;
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memset(&args, 0, sizeof(args));
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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if (encoder->crtc == crtc) {
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radeon_encoder = to_radeon_encoder(encoder);
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@ -718,68 +797,10 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
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radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
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&ref_div, &post_div);
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index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
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if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
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&crev))
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return;
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atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
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encoder_mode, radeon_encoder->encoder_id, mode->clock,
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ref_div, fb_div, frac_fb_div, post_div);
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switch (frev) {
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case 1:
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switch (crev) {
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case 1:
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args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
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args.v1.usRefDiv = cpu_to_le16(ref_div);
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args.v1.usFbDiv = cpu_to_le16(fb_div);
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args.v1.ucFracFbDiv = frac_fb_div;
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args.v1.ucPostDiv = post_div;
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args.v1.ucPpll = radeon_crtc->pll_id;
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args.v1.ucCRTC = radeon_crtc->crtc_id;
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args.v1.ucRefDivSrc = 1;
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break;
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case 2:
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args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
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args.v2.usRefDiv = cpu_to_le16(ref_div);
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args.v2.usFbDiv = cpu_to_le16(fb_div);
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args.v2.ucFracFbDiv = frac_fb_div;
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args.v2.ucPostDiv = post_div;
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args.v2.ucPpll = radeon_crtc->pll_id;
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args.v2.ucCRTC = radeon_crtc->crtc_id;
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args.v2.ucRefDivSrc = 1;
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break;
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case 3:
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args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
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args.v3.usRefDiv = cpu_to_le16(ref_div);
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args.v3.usFbDiv = cpu_to_le16(fb_div);
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args.v3.ucFracFbDiv = frac_fb_div;
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args.v3.ucPostDiv = post_div;
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args.v3.ucPpll = radeon_crtc->pll_id;
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args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2);
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args.v3.ucTransmitterId = radeon_encoder->encoder_id;
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args.v3.ucEncoderMode = encoder_mode;
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break;
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case 5:
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args.v5.ucCRTC = radeon_crtc->crtc_id;
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args.v5.usPixelClock = cpu_to_le16(mode->clock / 10);
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args.v5.ucRefDiv = ref_div;
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args.v5.usFbDiv = cpu_to_le16(fb_div);
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args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
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args.v5.ucPostDiv = post_div;
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args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
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args.v5.ucTransmitterID = radeon_encoder->encoder_id;
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args.v5.ucEncoderMode = encoder_mode;
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args.v5.ucPpll = radeon_crtc->pll_id;
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break;
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default:
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DRM_ERROR("Unknown table version %d %d\n", frev, crev);
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return;
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}
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break;
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default:
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DRM_ERROR("Unknown table version %d %d\n", frev, crev);
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return;
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}
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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@ -1191,6 +1212,24 @@ static void atombios_crtc_commit(struct drm_crtc *crtc)
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atombios_lock_crtc(crtc, ATOM_DISABLE);
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}
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static void atombios_crtc_disable(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
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switch (radeon_crtc->pll_id) {
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case ATOM_PPLL1:
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case ATOM_PPLL2:
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/* disable the ppll */
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atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
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0, 0, ATOM_DISABLE, 0, 0, 0, 0);
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break;
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default:
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break;
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}
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radeon_crtc->pll_id = -1;
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}
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static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
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.dpms = atombios_crtc_dpms,
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.mode_fixup = atombios_crtc_mode_fixup,
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@ -1199,6 +1238,7 @@ static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
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.prepare = atombios_crtc_prepare,
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.commit = atombios_crtc_commit,
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.load_lut = radeon_crtc_load_lut,
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.disable = atombios_crtc_disable,
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};
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void radeon_atombios_init_crtc(struct drm_device *dev,
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