mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-29 22:16:47 +07:00
drm/nvd0/disp: tidy up what we have so far
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
ee41779e76
commit
37b034a64b
@ -23,12 +23,12 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
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nva3_copy.o nvc0_copy.o \
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nv31_mpeg.o nv50_mpeg.o \
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nv04_instmem.o nv50_instmem.o nvc0_instmem.o \
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nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o \
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nv50_cursor.o nv50_display.o \
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nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \
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nv04_crtc.o nv04_display.o nv04_cursor.o \
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nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o \
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nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o \
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nv50_cursor.o nv50_display.o \
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nvd0_display.o \
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nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o \
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nv10_gpio.o nv50_gpio.o \
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nv50_calc.o \
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nv04_pm.o nv50_pm.o nva3_pm.o nvc0_pm.o \
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@ -31,13 +31,10 @@
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#include "nouveau_connector.h"
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#include "nouveau_encoder.h"
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#include "nouveau_crtc.h"
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#include "nouveau_dma.h"
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#include "nouveau_fb.h"
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#include "nv50_display.h"
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#define MEM_SYNC 0xe0000001
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#define MEM_VRAM 0xe0010000
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#include "nouveau_dma.h"
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struct nvd0_display {
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struct nouveau_gpuobj *mem;
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struct {
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@ -56,7 +53,7 @@ nvd0_display(struct drm_device *dev)
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return dev_priv->engine.display.priv;
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}
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static int
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static inline int
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evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
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{
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int ret = 0;
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@ -237,7 +234,7 @@ nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update)
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evo_data(push, 0x85000000);
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evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
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evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
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evo_data(push, MEM_VRAM);
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evo_data(push, NvEvoVRAM);
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} else {
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evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
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evo_data(push, 0x05000000);
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@ -295,7 +292,7 @@ nvd0_crtc_commit(struct drm_crtc *crtc)
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evo_data(push, 0x00000000);
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evo_data(push, 0x00000000);
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evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
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evo_data(push, MEM_VRAM);
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evo_data(push, NvEvoVRAM);
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evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
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evo_data(push, 0xffffff00);
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evo_kick(push, crtc->dev, 0);
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@ -958,23 +955,6 @@ nvd0_sor_create(struct drm_connector *connector, struct dcb_entry *dcbe)
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/******************************************************************************
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* IRQ
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*****************************************************************************/
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static void
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debug_irq(struct drm_device *dev, int i)
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{
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if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) {
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NV_INFO(dev, "PDISP: modeset req %d\n", i);
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NV_INFO(dev, " STAT: 0x%08x 0x%08x 0x%08x\n",
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nv_rd32(dev, 0x6101d0),
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nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
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for (i = 0; i < 8; i++) {
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NV_INFO(dev, " %s%d: 0x%08x 0x%08x\n",
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i < 4 ? "DAC" : "SOR", i,
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nv_rd32(dev, 0x640180 + (i * 0x20)),
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nv_rd32(dev, 0x660180 + (i * 0x20)));
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}
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}
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}
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static struct dcb_entry *
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lookup_dcb(struct drm_device *dev, int id, u32 mc)
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{
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@ -1009,20 +989,11 @@ lookup_dcb(struct drm_device *dev, int id, u32 mc)
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}
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static void
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nvd0_display_unk1_handler(struct drm_device *dev)
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nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask)
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{
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struct dcb_entry *dcb;
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u32 mask, crtc;
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int i;
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mask = nv_rd32(dev, 0x6101d4);
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crtc = 0;
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if (!mask) {
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mask = nv_rd32(dev, 0x6109d4);
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crtc = 1;
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}
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debug_irq(dev, 1);
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for (i = 0; mask && i < 8; i++) {
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u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
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if (!(mcc & (1 << crtc)))
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@ -1041,21 +1012,12 @@ nvd0_display_unk1_handler(struct drm_device *dev)
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}
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static void
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nvd0_display_unk2_handler(struct drm_device *dev)
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nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
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{
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struct dcb_entry *dcb;
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u32 mask, crtc, pclk;
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u32 or, tmp;
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u32 or, tmp, pclk;
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int i;
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mask = nv_rd32(dev, 0x6101d4);
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crtc = 0;
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if (!mask) {
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mask = nv_rd32(dev, 0x6109d4);
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crtc = 1;
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}
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debug_irq(dev, 2);
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for (i = 0; mask && i < 8; i++) {
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u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
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if (!(mcc & (1 << crtc)))
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@ -1113,20 +1075,11 @@ nvd0_display_unk2_handler(struct drm_device *dev)
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}
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static void
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nvd0_display_unk4_handler(struct drm_device *dev)
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nvd0_display_unk4_handler(struct drm_device *dev, u32 crtc, u32 mask)
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{
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struct dcb_entry *dcb;
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u32 mask, crtc;
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int pclk, i;
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mask = nv_rd32(dev, 0x6101d4);
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crtc = 0;
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if (!mask) {
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mask = nv_rd32(dev, 0x6109d4);
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crtc = 1;
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}
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debug_irq(dev, 4);
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pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
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for (i = 0; mask && i < 8; i++) {
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@ -1152,13 +1105,35 @@ nvd0_display_bh(unsigned long data)
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{
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struct drm_device *dev = (struct drm_device *)data;
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struct nvd0_display *disp = nvd0_display(dev);
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u32 mask, crtc;
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int i;
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if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) {
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NV_INFO(dev, "PDISP: modeset req %d\n", disp->modeset);
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NV_INFO(dev, " STAT: 0x%08x 0x%08x 0x%08x\n",
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nv_rd32(dev, 0x6101d0),
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nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
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for (i = 0; i < 8; i++) {
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NV_INFO(dev, " %s%d: 0x%08x 0x%08x\n",
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i < 4 ? "DAC" : "SOR", i,
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nv_rd32(dev, 0x640180 + (i * 0x20)),
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nv_rd32(dev, 0x660180 + (i * 0x20)));
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}
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}
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mask = nv_rd32(dev, 0x6101d4);
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crtc = 0;
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if (!mask) {
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mask = nv_rd32(dev, 0x6109d4);
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crtc = 1;
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}
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if (disp->modeset & 0x00000001)
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nvd0_display_unk1_handler(dev);
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nvd0_display_unk1_handler(dev, crtc, mask);
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if (disp->modeset & 0x00000002)
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nvd0_display_unk2_handler(dev);
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nvd0_display_unk2_handler(dev, crtc, mask);
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if (disp->modeset & 0x00000004)
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nvd0_display_unk4_handler(dev);
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nvd0_display_unk4_handler(dev, crtc, mask);
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}
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static void
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@ -1324,7 +1299,7 @@ nvd0_display_init(struct drm_device *dev)
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if (!push)
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return -EBUSY;
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evo_mthd(push, 0x0088, 1);
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evo_data(push, MEM_SYNC);
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evo_data(push, NvEvoSync);
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evo_mthd(push, 0x0084, 1);
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evo_data(push, 0x00000000);
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evo_mthd(push, 0x0084, 1);
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@ -1430,7 +1405,7 @@ nvd0_display_create(struct drm_device *dev)
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nv_wo32(disp->mem, 0x100c, 0x00000000);
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nv_wo32(disp->mem, 0x1010, 0x00000000);
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nv_wo32(disp->mem, 0x1014, 0x00000000);
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nv_wo32(disp->mem, 0x0000, MEM_SYNC);
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nv_wo32(disp->mem, 0x0000, NvEvoSync);
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nv_wo32(disp->mem, 0x0004, (0x1000 << 9) | 0x00000001);
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nv_wo32(disp->mem, 0x1020, 0x00000049);
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@ -1439,7 +1414,7 @@ nvd0_display_create(struct drm_device *dev)
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nv_wo32(disp->mem, 0x102c, 0x00000000);
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nv_wo32(disp->mem, 0x1030, 0x00000000);
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nv_wo32(disp->mem, 0x1034, 0x00000000);
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nv_wo32(disp->mem, 0x0008, MEM_VRAM);
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nv_wo32(disp->mem, 0x0008, NvEvoVRAM);
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nv_wo32(disp->mem, 0x000c, (0x1020 << 9) | 0x00000001);
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nv_wo32(disp->mem, 0x1040, 0x00000009);
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