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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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mvebu clock fixes for v3.14
- kirkwood, dove, armada-xp, armada-370 - force clock init order broken by sorting DT ocp nodes by address - fixes boot failures on affected platforms -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJS9mjbAAoJEP45WPkGe8ZnkcYP/0R2kke0sfzO/KKbTH9srAh1 OUDmVPguhGCZfhsJoaQyzUE9vf3dX0G3ZuZlriPIlaFoZp8U2QTvMspG0byrHrTv V1+Wt9yKYrIRcJm0kfFNPwON+WaZk004TqSR7aCVm7CqRrgKQ91wQ5o42coPBznZ Vfu13wM9oHwy2nT/w42laHZOQuMYYW0GQYsdzxECPledURA0dh/iW8UZ48WMoCjO 9QWLGO3NOm+xR3n9KsfIkQ44WbL3FGjzRWq62jPjtquanMR4h0nOSTVEGPveqSbw o/OA8Ft/j3Bcfj7uGYeQ7GxHW0kpA50e8rzFQ8RYaRsGVBI5bTNsGzk17eEUswqZ uXm0V+MV8fklVhRtRMU93gYvvhi4adCj9DauLEhevKBW9XDaAkEi577uCjnpOijF aXg9TqV5mmUuH3iapMb/QD2+MOkL9qQOjOHQUBUAv6fUZxNwyZoNYP7KEmvDvMyY nyZv4Ve7u9ock2ZNUVn7COv9/9HTwusa1Z3Woi9eKy2eWriNM4bxcqP89601cZid HJbn6iwG5zDkhOqf9rgcrWVQPU6jBu/7ZKA2zYtbOUTsrxTOuMSMnTNO0XqZ2L27 Hu1h9ezlJPQBD6tQcxjpSk7s8LB3iZYExQyNbIeGRbKdPQXg/3N05mMb4xWZ/Y2d hTgivwr3/voXq1s+ZHbk =MWFb -----END PGP SIGNATURE----- Merge tag 'mvebu-clk-fixes-3.14' of git://git.infradead.org/linux-mvebu into clk-fixes mvebu clock fixes for v3.14 - kirkwood, dove, armada-xp, armada-370 - force clock init order broken by sorting DT ocp nodes by address - fixes boot failures on affected platforms
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commit
37a4493ee7
@ -141,13 +141,6 @@ static const struct coreclk_soc_desc a370_coreclks = {
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.num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
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};
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static void __init a370_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &a370_coreclks);
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}
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CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock",
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a370_coreclk_init);
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/*
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* Clock Gating Control
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*/
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@ -168,9 +161,15 @@ static const struct clk_gating_soc_desc a370_gating_desc[] __initconst = {
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{ }
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};
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static void __init a370_clk_gating_init(struct device_node *np)
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static void __init a370_clk_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, a370_gating_desc);
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struct device_node *cgnp =
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of_find_compatible_node(NULL, NULL, "marvell,armada-370-gating-clock");
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mvebu_coreclk_setup(np, &a370_coreclks);
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if (cgnp)
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mvebu_clk_gating_setup(cgnp, a370_gating_desc);
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}
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CLK_OF_DECLARE(a370_clk_gating, "marvell,armada-370-gating-clock",
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a370_clk_gating_init);
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CLK_OF_DECLARE(a370_clk, "marvell,armada-370-core-clock", a370_clk_init);
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@ -158,13 +158,6 @@ static const struct coreclk_soc_desc axp_coreclks = {
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.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
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};
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static void __init axp_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &axp_coreclks);
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}
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CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock",
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axp_coreclk_init);
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/*
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* Clock Gating Control
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*/
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@ -202,9 +195,14 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
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{ }
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};
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static void __init axp_clk_gating_init(struct device_node *np)
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static void __init axp_clk_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, axp_gating_desc);
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struct device_node *cgnp =
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of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
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mvebu_coreclk_setup(np, &axp_coreclks);
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if (cgnp)
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mvebu_clk_gating_setup(cgnp, axp_gating_desc);
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}
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CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock",
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axp_clk_gating_init);
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CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
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@ -154,12 +154,6 @@ static const struct coreclk_soc_desc dove_coreclks = {
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.num_ratios = ARRAY_SIZE(dove_coreclk_ratios),
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};
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static void __init dove_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &dove_coreclks);
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}
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CLK_OF_DECLARE(dove_core_clk, "marvell,dove-core-clock", dove_coreclk_init);
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/*
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* Clock Gating Control
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*/
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@ -186,9 +180,14 @@ static const struct clk_gating_soc_desc dove_gating_desc[] __initconst = {
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{ }
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};
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static void __init dove_clk_gating_init(struct device_node *np)
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static void __init dove_clk_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, dove_gating_desc);
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struct device_node *cgnp =
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of_find_compatible_node(NULL, NULL, "marvell,dove-gating-clock");
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mvebu_coreclk_setup(np, &dove_coreclks);
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if (cgnp)
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mvebu_clk_gating_setup(cgnp, dove_gating_desc);
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}
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CLK_OF_DECLARE(dove_clk_gating, "marvell,dove-gating-clock",
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dove_clk_gating_init);
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CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init);
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@ -193,13 +193,6 @@ static const struct coreclk_soc_desc kirkwood_coreclks = {
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.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
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};
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static void __init kirkwood_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &kirkwood_coreclks);
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}
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CLK_OF_DECLARE(kirkwood_core_clk, "marvell,kirkwood-core-clock",
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kirkwood_coreclk_init);
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static const struct coreclk_soc_desc mv88f6180_coreclks = {
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.get_tclk_freq = kirkwood_get_tclk_freq,
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.get_cpu_freq = mv88f6180_get_cpu_freq,
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@ -208,13 +201,6 @@ static const struct coreclk_soc_desc mv88f6180_coreclks = {
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.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
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};
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static void __init mv88f6180_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &mv88f6180_coreclks);
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}
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CLK_OF_DECLARE(mv88f6180_core_clk, "marvell,mv88f6180-core-clock",
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mv88f6180_coreclk_init);
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/*
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* Clock Gating Control
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*/
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@ -239,9 +225,21 @@ static const struct clk_gating_soc_desc kirkwood_gating_desc[] __initconst = {
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{ }
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};
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static void __init kirkwood_clk_gating_init(struct device_node *np)
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static void __init kirkwood_clk_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, kirkwood_gating_desc);
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struct device_node *cgnp =
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of_find_compatible_node(NULL, NULL, "marvell,kirkwood-gating-clock");
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if (of_device_is_compatible(np, "marvell,mv88f6180-core-clock"))
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mvebu_coreclk_setup(np, &mv88f6180_coreclks);
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else
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mvebu_coreclk_setup(np, &kirkwood_coreclks);
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if (cgnp)
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mvebu_clk_gating_setup(cgnp, kirkwood_gating_desc);
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}
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CLK_OF_DECLARE(kirkwood_clk_gating, "marvell,kirkwood-gating-clock",
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kirkwood_clk_gating_init);
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CLK_OF_DECLARE(kirkwood_clk, "marvell,kirkwood-core-clock",
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kirkwood_clk_init);
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CLK_OF_DECLARE(mv88f6180_clk, "marvell,mv88f6180-core-clock",
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kirkwood_clk_init);
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