mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-29 22:16:47 +07:00
ARM: 6295/1: fix U300 apb_pclk split
This fixes a regression due to the new apb_pclk stuff in the U300 platform, makes it run by splitting the apb clock off the single UART clocks. For the MMCI and PL022 clocks we don't split them: these are actually hardwired to the same clock terminal and will thus simply have a double reference count and will be referenced twice. We also move clock registration to .init_irq() so they are available early enough for probing to be successful and remove the earlier quirk to clock primecells during PrimeCell registration. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Linus Walleij
Russell King
parent
c2fab1242a
commit
379aae5d6c
@ -947,6 +947,10 @@ static struct clk fast_clk = {
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.lock = __SPIN_LOCK_UNLOCKED(fast_clk.lock),
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};
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/*
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* The MMCI apb_pclk is hardwired to the same terminal as the
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* external MCI clock. Thus this will be referenced twice.
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*/
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static struct clk mmcsd_clk = {
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.name = "MCLK",
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.parent = &fast_clk,
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@ -1024,6 +1028,10 @@ static struct clk i2c1_clk = {
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.lock = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock),
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};
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/*
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* The SPI apb_pclk is hardwired to the same terminal as the
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* external SPI clock. Thus this will be referenced twice.
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*/
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static struct clk spi_clk = {
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.name = "SPI",
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.parent = &fast_clk,
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@ -1040,10 +1048,9 @@ static struct clk spi_clk = {
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};
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#ifdef CONFIG_MACH_U300_BS335
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static struct clk uart1_clk = {
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.name = "UART1",
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static struct clk uart1_pclk = {
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.name = "UART1_PCLK",
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.parent = &fast_clk,
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.rate = 13000000,
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.hw_ctrld = false,
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.reset = true,
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.res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
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@ -1051,6 +1058,14 @@ static struct clk uart1_clk = {
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.clk_val = U300_SYSCON_SBCER_UART1_CLK_EN,
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.enable = syscon_clk_enable,
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.disable = syscon_clk_disable,
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.lock = __SPIN_LOCK_UNLOCKED(uart1_pclk.lock),
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};
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/* This one is hardwired to PLL13 */
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static struct clk uart1_clk = {
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.name = "UART1_CLK",
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.rate = 13000000,
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.hw_ctrld = true,
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.lock = __SPIN_LOCK_UNLOCKED(uart1_clk.lock),
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};
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#endif
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@ -1085,11 +1100,9 @@ static struct clk wdog_clk = {
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.lock = __SPIN_LOCK_UNLOCKED(wdog_clk.lock),
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};
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/* This one is hardwired to PLL13 */
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static struct clk uart_clk = {
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.name = "UARTCLK",
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static struct clk uart0_pclk = {
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.name = "UART0_PCLK",
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.parent = &slow_clk,
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.rate = 13000000,
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.hw_ctrld = false,
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.reset = true,
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.res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
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@ -1097,7 +1110,16 @@ static struct clk uart_clk = {
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.clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
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.enable = syscon_clk_enable,
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.disable = syscon_clk_disable,
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.lock = __SPIN_LOCK_UNLOCKED(uart_clk.lock),
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.lock = __SPIN_LOCK_UNLOCKED(uart0_pclk.lock),
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};
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/* This one is hardwired to PLL13 */
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static struct clk uart0_clk = {
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.name = "UART0_CLK",
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.parent = &slow_clk,
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.rate = 13000000,
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.hw_ctrld = true,
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.lock = __SPIN_LOCK_UNLOCKED(uart0_clk.lock),
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};
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static struct clk keypad_clk = {
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@ -1212,23 +1234,24 @@ static struct clk ppm_clk = {
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};
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#endif
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static struct clk dummy_apb_pclk;
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#define DEF_LOOKUP(devid, clkref) \
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{ \
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.dev_id = devid, \
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.clk = clkref, \
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}
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#define DEF_LOOKUP_CON(devid, conid, clkref) \
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{ \
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.dev_id = devid, \
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.con_id = conid, \
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.clk = clkref, \
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}
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/*
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* Here we only define clocks that are meaningful to
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* look up through clockdevice.
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*/
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static struct clk_lookup lookups[] = {
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{
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.con_id = "apb_pclk",
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.clk = &dummy_apb_pclk,
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},
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/* Connected directly to the AMBA bus */
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DEF_LOOKUP("amba", &amba_clk),
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DEF_LOOKUP("cpu", &cpu_clk),
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@ -1247,11 +1270,14 @@ static struct clk_lookup lookups[] = {
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/* AHB bridge clocks */
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DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk),
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DEF_LOOKUP("intcon", &intcon_clk),
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DEF_LOOKUP_CON("intcon", "apb_pclk", &intcon_clk),
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DEF_LOOKUP("mspro", &mspro_clk),
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DEF_LOOKUP("pl172", &emif_clk),
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DEF_LOOKUP_CON("pl172", "apb_pclk", &emif_clk),
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/* FAST bridge clocks */
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DEF_LOOKUP("fast", &fast_clk),
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DEF_LOOKUP("mmci", &mmcsd_clk),
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DEF_LOOKUP_CON("mmci", "apb_pclk", &mmcsd_clk),
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/*
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* The .0 and .1 identifiers on these comes from the platform device
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* .id field and are assigned when the platform devices are registered.
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@ -1261,13 +1287,16 @@ static struct clk_lookup lookups[] = {
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DEF_LOOKUP("stu300.0", &i2c0_clk),
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DEF_LOOKUP("stu300.1", &i2c1_clk),
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DEF_LOOKUP("pl022", &spi_clk),
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DEF_LOOKUP_CON("pl022", "apb_pclk", &spi_clk),
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#ifdef CONFIG_MACH_U300_BS335
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DEF_LOOKUP("uart1", &uart1_clk),
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DEF_LOOKUP_CON("uart1", "apb_pclk", &uart1_pclk),
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#endif
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/* SLOW bridge clocks */
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DEF_LOOKUP("slow", &slow_clk),
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DEF_LOOKUP("coh901327_wdog", &wdog_clk),
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DEF_LOOKUP("uart0", &uart_clk),
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DEF_LOOKUP("uart0", &uart0_clk),
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DEF_LOOKUP_CON("uart0", "apb_pclk", &uart0_pclk),
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DEF_LOOKUP("apptimer", &app_timer_clk),
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DEF_LOOKUP("coh901461-keypad", &keypad_clk),
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DEF_LOOKUP("u300-gpio", &gpio_clk),
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@ -1286,46 +1315,6 @@ static void __init clk_register(void)
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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}
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/*
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* These are the clocks for cells registered as primecell drivers
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* on the AMBA bus. These must be on during AMBA device registration
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* since the bus probe will attempt to read magic configuration
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* registers for these devices. If they are deactivated these probes
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* will fail.
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*
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*
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* Please note that on emif, both RAM and NAND is connected in dual
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* RAM phones. On single RAM phones, ram is on semi and NAND on emif.
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*
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*/
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void u300_clock_primecells(void)
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{
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clk_enable(&intcon_clk);
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clk_enable(&uart_clk);
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#ifdef CONFIG_MACH_U300_BS335
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clk_enable(&uart1_clk);
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#endif
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clk_enable(&spi_clk);
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clk_enable(&mmcsd_clk);
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}
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EXPORT_SYMBOL(u300_clock_primecells);
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void u300_unclock_primecells(void)
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{
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clk_disable(&intcon_clk);
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clk_disable(&uart_clk);
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#ifdef CONFIG_MACH_U300_BS335
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clk_disable(&uart1_clk);
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#endif
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clk_disable(&spi_clk);
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clk_disable(&mmcsd_clk);
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}
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EXPORT_SYMBOL(u300_unclock_primecells);
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/*
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* The interrupt controller is enabled before the clock API is registered.
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*/
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@ -1344,6 +1333,7 @@ void u300_enable_timer_clock(void)
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}
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EXPORT_SYMBOL(u300_enable_timer_clock);
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#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
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/*
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* The following makes it possible to view the status (especially
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@ -1385,11 +1375,13 @@ static struct clk *clks[] = {
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&spi_clk,
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#ifdef CONFIG_MACH_U300_BS335
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&uart1_clk,
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&uart1_pclk,
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#endif
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/* SLOW bridge clocks */
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&slow_clk,
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&wdog_clk,
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&uart_clk,
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&uart0_clk,
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&uart0_pclk,
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&app_timer_clk,
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&keypad_clk,
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&gpio_clk,
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@ -1430,7 +1422,7 @@ static int u300_clocks_show(struct seq_file *s, void *data)
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chars++;
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}
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cdp[32] = '\0';
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if (clk->get_rate)
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if (clk->get_rate || clk->rate != 0)
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seq_printf(s,
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"%s%s\t%s\t%d\t%s\t%lu Hz\n",
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&cdp[0],
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@ -1439,7 +1431,7 @@ static int u300_clocks_show(struct seq_file *s, void *data)
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clk->usecount ? "ON" : "OFF",
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clk->usecount,
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clk->hw_ctrld ? "YES" : "NO ",
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clk->get_rate(clk));
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clk_get_rate(clk));
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else
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seq_printf(s,
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"%s%s\t%s\t%d\t%s\t" \
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@ -1483,7 +1475,7 @@ static int __init init_clk_read_debugfs(void)
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module_init(init_clk_read_debugfs);
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#endif
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static int __init u300_clock_init(void)
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int __init u300_clock_init(void)
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{
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u16 val;
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@ -1520,10 +1512,8 @@ static int __init u300_clock_init(void)
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*/
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syscon_block_reset_disable(&semi_clk);
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syscon_block_reset_disable(&emif_clk);
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semi_clk.enable(&semi_clk);
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emif_clk.enable(&emif_clk);
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clk_enable(&semi_clk);
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clk_enable(&emif_clk);
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return 0;
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}
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/* initialize clocking early to be available later in the boot */
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core_initcall(u300_clock_init);
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@ -45,9 +45,8 @@ struct clk {
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void (*disable) (struct clk *);
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};
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void u300_clock_primecells(void);
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void u300_unclock_primecells(void);
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void u300_enable_intcon_clock(void);
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void u300_enable_timer_clock(void);
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int u300_clock_init(void);
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#endif
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@ -1479,6 +1479,9 @@ void __init u300_init_irq(void)
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u32 mask[2] = {0, 0};
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int i;
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/* initialize clocking early, we want to clock the INTCON */
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u300_clock_init();
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for (i = 0; i < NR_IRQS; i++)
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set_bit(i, (unsigned long *) &mask[0]);
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u300_enable_intcon_clock();
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@ -1635,12 +1638,10 @@ void __init u300_init_devices(void)
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u300_spi_init(&pl022_device);
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/* Register the AMBA devices in the AMBA bus abstraction layer */
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u300_clock_primecells();
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for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
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struct amba_device *d = amba_devs[i];
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amba_device_register(d, &iomem_resource);
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}
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u300_unclock_primecells();
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u300_assign_physmem();
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